公开(公告)号：US20170287103A1

公开(公告)日：2017-10-05

申请号：US15628480

申请日：2017-06-20

Applicant: Google Inc.

Inventor： Albert Meixner ,  Hyunchul Park ,  William R. Mark ,  Daniel Frederic Finchelstein ,  Ofer Shacham

IPC: G06T1/20 ,  G06F9/45 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F8/447 ,  G06F9/5077

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.

公开(公告)号：US20180007303A1

公开(公告)日：2018-01-04

申请号：US15628527

申请日：2017-06-20

Applicant: Google Inc.

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/374 ,  H04N5/341

CPC classification number: H04N5/3742 ,  G06F5/015 ,  G06F12/0207 ,  G06F17/16 ,  G06T1/20 ,  H04N5/341

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

公开(公告)号：US20180005075A1

公开(公告)日：2018-01-04

申请号：US15631906

申请日：2017-06-23

Applicant: Google Inc.

Inventor： Ofer Shacham ,  David Patterson ,  William R. Mark ,  Albert Meixner ,  Daniel Frederic Finchelstein ,  Jason Rupert Redgrave

IPC: G06K9/56 ,  G06T5/20 ,  G06K9/46

Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.

公开(公告)号：US20160314555A1

公开(公告)日：2016-10-27

申请号：US14694828

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Albert Meixner ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  David Patterson ,  Neeti Desai ,  Donald Stark ,  Edward T. Chang ,  William R. Mark

IPC: G06T1/20 ,  G06T1/60 ,  H04N5/91 ,  H04N5/378

CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N5/378 ,  H04N5/91

Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

Abstract translation: 描述了一种装置。 该装置包括图像处理单元。 图像处理单元包括网络。 图像处理单元包括多个模板处理器电路，每个模板处理器电路各自包括耦合到二维移位寄存器阵列结构的执行单元通道的阵列，以通过执行程序代码来同时处理多个重叠模版。 图像处理单元包括分别耦合在多个模板处理器和网络之间的多个片材生成器。 片材生成器将图像数据的输入线组分解成图像数据的输入片以供模板处理器处理，并且从从模版处理器接收的图像数据的输出片材中形成图像数据的输出线组。 图像处理单元包括耦合到网络的多个行缓冲单元，以在从生成模板处理器到消耗模板处理器的方向上传递线组，以实现整个程序流程。