Integrated heater structures in a photonic integrated circuit for solder attachment applications

    公开(公告)号:US10895702B2

    公开(公告)日:2021-01-19

    申请号:US16371800

    申请日:2019-04-01

    Applicant: Google LLC

    Abstract: An apparatus including a photonic integrated circuit (PIC) coupled to an optical bench is disclosed. The PIC includes at least one grating coupler disposed thereon and the optical bench includes an optical system disposed thereon. The apparatus also includes an integrated heater at an upper surface of the PIC under the optical bench or at a bottom surface of the optical bench over the PIC. The apparatus also includes a layer of solder disposed between the PIC and the optical bench for coupling the bottom surface of the optical bench to the PIC. In some implementations, the layer of solder is in thermal communication with the integrated heater.

    Secondary grid plates for optical switching applications

    公开(公告)号:US11662527B2

    公开(公告)日:2023-05-30

    申请号:US17189985

    申请日:2021-03-02

    Applicant: Google LLC

    CPC classification number: G02B6/353 G02B6/3518 G02B6/3598

    Abstract: An optical assembly includes a light source for providing a beam of light, a lens system configured to expand and collimate the beam of light, and a configurable beam injector, wherein the beam injector contains a first grid plate and a second grid plate to block individual beams of light. The first grid plate and the second grid plate may be configured such that each grid plate respectively corresponds to particular MEMS mirrors. The grid plates can be configured to have pathways that allow for beams of light to be passed through and other pathways which are blocked to prevent the passage of light. The first grid plate and second grid plate may thus block or allow for transmission of beams of lights to those particular MEMS mirrors. The second grid plate can be configured to be easily swappable during or removable to allow for a different set of beams of light, corresponding to a different set of MEMS mirrors, to be blocked. The second grid plate can be configured to be rotated or slid linearly within a housing.

    Laser light source co-packaged with photonic integrated circuit and substrate

    公开(公告)号:US11564312B2

    公开(公告)日:2023-01-24

    申请号:US17034867

    申请日:2020-09-28

    Applicant: Google LLC

    Abstract: The present disclosure provides for an example integrated optics assembly. The integrated optics assembly may include an optics mount, a substrate including a heat sink, and a photonic integrated circuit (“PIC”). The optics mount may be adapted to support a light source on a first end of the optics mount. The first end of the optics mount may be coupled to a region of the substrate including the heat sink. The heat sink may remove or dissipate the heat produced by the light source. A second end of the optics mount may be coupled to the PIC such that the optics mount extends between the substrate and the PIC. This may decrease the amount of space the optics mount takes up on the PIC thereby allowing the overall size of the PIC to be decreased. Decreasing the size of the PIC may allow for more PICS per wafer.

    Laser Light Source Co-Packaged with Photonic Integrated Circuit and Substrate

    公开(公告)号:US20220104342A1

    公开(公告)日:2022-03-31

    申请号:US17034867

    申请日:2020-09-28

    Applicant: Google LLC

    Abstract: The present disclosure provides for an example integrated optics assembly. The integrated optics assembly may include an optics mount, a substrate including a heat sink, and a photonic integrated circuit (“PIC”). The optics mount may be adapted to support a light source on a first end of the optics mount. The first end of the optics mount may be coupled to a region of the substrate including the heat sink. The heat sink may remove or dissipate the heat produced by the light source. A second end of the optics mount may be coupled to the PIC such that the optics mount extends between the substrate and the PIC. This may decrease the amount of space the optics mount takes up on the PIC thereby allowing the overall size of the PIC to be decreased. Decreasing the size of the PIC may allow for more PICS per wafer.

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