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公开(公告)号:US20230267089A1
公开(公告)日:2023-08-24
申请号:US18112740
申请日:2023-02-22
Applicant: Google LLC
Inventor: Santanu Dasgupta , Durgaprasad V. Ayyadevara , Bor Chan , Prashant R. Chandra , Bok Knun Randolph Chung , Max Kamenetsky , Rajeev Koodli , Shahin Valoth
CPC classification number: G06F13/385 , G06F13/122 , G06F2213/0038
Abstract: The present disclosure provides a compute platform architecture for virtualized and cloud native network functions. The architecture uses a reduced instruction set computer-based general purpose processor along with multiple special purpose accelerators and an integrated network interface card. As such, the architecture can accommodate multiple hundreds of gigabits of input/output.
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公开(公告)号:US12259841B2
公开(公告)日:2025-03-25
申请号:US18237171
申请日:2023-08-23
Applicant: Google LLC
Inventor: Ian Kenneth Coolidge , Shahin Valoth
IPC: G06F13/42
Abstract: The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.
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公开(公告)号:US20250068581A1
公开(公告)日:2025-02-27
申请号:US18237171
申请日:2023-08-23
Applicant: Google LLC
Inventor: Ian Kenneth Coolidge , Shahin Valoth
IPC: G06F13/42
Abstract: The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.
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