Passive clock synchronization for timing

    公开(公告)号:US12259841B2

    公开(公告)日:2025-03-25

    申请号:US18237171

    申请日:2023-08-23

    Applicant: Google LLC

    Abstract: The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.

    Passive Clock Synchronization For Timing

    公开(公告)号:US20250068581A1

    公开(公告)日:2025-02-27

    申请号:US18237171

    申请日:2023-08-23

    Applicant: Google LLC

    Abstract: The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.

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