公开(公告)号：US10592431B2

公开(公告)日：2020-03-17

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

公开(公告)号：US20200050553A1

公开(公告)日：2020-02-13

申请号：US16101997

申请日：2018-08-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Izzat El Hajj ,  Alexander Marshall Merritt ,  Gerd Zellweger ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F12/109 ,  G06F12/1009

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.