INTEGRATED CIRCUIT WITH HOT PLUG CONTROL
    1.
    发明申请

    公开(公告)号:US20200042484A1

    公开(公告)日:2020-02-06

    申请号:US16050144

    申请日:2018-07-31

    Abstract: A system comprising: a first host and a second host; and an integrated circuit comprising: a first bus and a second bus physically separate and isolated from the first bus; a first host interface to connect the first host to the first bus and a second host interface to connect the second host to the second bus; and a hot plug control channel including first and second hot plug control registers, wherein each of the hot plug control registers is connectable to a hot pluggable device; wherein the hot plug control channel is to connect the first bus to the first and second hot plug control register to thereby connect the first host to the first and second hot plug control register, and is to connect the second bus to the first and second hot plug control register to thereby connect the second host to the first and second hot plug control register.

    PCIe Connectors
    2.
    发明申请
    PCIe Connectors 审中-公开

    公开(公告)号:US20180217957A1

    公开(公告)日:2018-08-02

    申请号:US15418361

    申请日:2017-01-27

    Abstract: An example electronic device may include a peripheral component interconnect express (PCIe) connector that includes a number of lane ports that may be arranged in a row. Physical lane numbers of the lane ports in a first half of the row may be in either an ascending order or a descending order from a first end of the row toward a middle of the row. Physical lane numbers of the lane ports in a second half of the row may be in either a descending order or an ascending order from the middle of the row toward a second end of the row. The order of the second half may be ascending when the order of the first half is descending, and the order of the second half may be descending when the order of the first half is ascending.

    PCIe connectors
    3.
    发明授权

    公开(公告)号:US10585831B2

    公开(公告)日:2020-03-10

    申请号:US15418361

    申请日:2017-01-27

    Abstract: An example electronic device may include a peripheral component interconnect express (PCIe) connector that includes a number of lane ports that may be arranged in a row. Physical lane numbers of the lane ports in a first half of the row may be in either an ascending order or a descending order from a first end of the row toward a middle of the row. Physical lane numbers of the lane ports in a second half of the row may be in either a descending order or an ascending order from the middle of the row toward a second end of the row. The order of the second half may be ascending when the order of the first half is descending, and the order of the second half may be descending when the order of the first half is ascending.

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