公开(公告)号：US20180301187A1

公开(公告)日：2018-10-18

申请号：US15768546

申请日：2015-10-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： James S IGNOWSKI ,  Martin FOLTIN ,  Yoocharn JEON

IPC: G11C13/00

Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.