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    MEMORY CONTROLLERS
    2.
    发明申请
    MEMORY CONTROLLERS 有权

    公开(公告)号：US20170249987A1

    公开(公告)日：2017-08-31

    申请号：US15500074

    申请日：2014-11-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Yoocharn JEON ,  James S. IGNOWSKI

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G06F13/1668 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.

    ENCODING DATA IN A MEMORY ARRAY
    3.
    发明申请
    ENCODING DATA IN A MEMORY ARRAY 审中-公开
    在存储器阵列中编码数据

    公开(公告)号：US20160342352A1

    公开(公告)日：2016-11-24

    申请号：US15114939

    申请日：2014-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B LESARTRE ,  Naveen MURALIMANOHAR ,  Yoocharn JEON

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0689 ,  G06F12/023 ,  G06F2212/1028 ,  G06F2212/1036 ,  G06F2212/401 ,  G11C7/1006 ,  Y02D10/13

    Abstract: A method for encoding data in a memory array is described. The method includes receiving data to be stored in the memory array. The method also includes encoding the data, to generate a number of encoded data versions. The method also includes selecting, based on a number of optimization heuristics, which of a number of data versions to store in the memory array. The number of data versions include the number of encoded data versions and the data. The method also includes indicating, in metadata associated with the data, the selected data version. The method also includes writing the selected data version, the metadata, or combination thereof, to the memory array.

    Abstract translation: 描述了一种用于对存储器阵列中的数据进行编码的方法。 该方法包括接收要存储在存储器阵列中的数据。 该方法还包括对数据进行编码，以生成多个编码数据版本。 该方法还包括基于多个优化启发式来选择存储在存储器阵列中的多个数据版本中的哪一个。 数据版本数量包括编码数据版本和数据的数量。 该方法还包括在与数据相关联的元数据中指示所选择的数据版本。 该方法还包括将所选数据版本，元数据或其组合写入存储器阵列。

    REFERENCE COLUMN SENSING FOR RESISTIVE MEMORY
    4.
    发明申请
    REFERENCE COLUMN SENSING FOR RESISTIVE MEMORY 审中-公开

    公开(公告)号：US20180301187A1

    公开(公告)日：2018-10-18

    申请号：US15768546

    申请日：2015-10-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： James S IGNOWSKI ,  Martin FOLTIN ,  Yoocharn JEON

    IPC: G11C13/00

    Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

    SIDEWALL SPACERS
    5.
    发明申请
    SIDEWALL SPACERS 有权

    公开(公告)号：US20170244029A1

    公开(公告)日：2017-08-24

    申请号：US15500085

    申请日：2015-01-09

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Hans S. CHO ,  Yoocharn JEON

    IPC: H01L45/00

    CPC classification number: H01L45/124 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1675

    Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.

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