IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS

    公开(公告)号:US20210229430A1

    公开(公告)日:2021-07-29

    申请号:US16769396

    申请日:2019-02-06

    Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

    IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS

    公开(公告)号:US20220349872A1

    公开(公告)日:2022-11-03

    申请号:US17865253

    申请日:2022-07-14

    Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

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