公开(公告)号：US07574638B2

公开(公告)日：2009-08-11

申请号：US11345897

申请日：2006-02-02

Applicant: Hae-Jin Song ,  Jin-Tae Joo

Inventor： Hae-Jin Song ,  Jin-Tae Joo

IPC: G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31725

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.

Abstract translation: 本发明提供能够使用一个测试引脚进行测试并且使用没有任何测试引脚的输入/输出引脚的半导体器件及其测试方法。 一个半导体器件包括用于输入/输出测试数据的测试引脚，用于响应于外部复位信号和时钟信号激活使能信号的操作模式控制器，用于通过所述时钟信号接收与时钟信号同步的串行数据的操作模式存储器 测试引脚以及响应于存储在操作模式存储器中的串行数据产生操作模式选择信号的操作模式解码器。 另一个半导体器件包括用于接收测试数据的输入/输出引脚，用于延迟复位信号的延迟复位信号发生器，响应于复位信号计数时钟信号的计数器以产生计数值;模式寄存器， 测试数据和用于向模式寄存器产生选择信号的解码器，以指定写入测试数据的模式寄存器中的位置。

公开(公告)号：US20060184847A1

公开(公告)日：2006-08-17

申请号：US11345897

申请日：2006-02-02

Applicant: Hae-Jin Song ,  Jin-Tae Joo

Inventor： Hae-Jin Song ,  Jin-Tae Joo

IPC: G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31725

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.

公开(公告)号：US07493440B2

公开(公告)日：2009-02-17

申请号：US11525389

申请日：2006-09-22

Applicant: Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

Inventor： Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

IPC: G06F13/14

CPC classification number: H04W52/287 ,  G06F1/3209 ,  G06F1/3237 ,  G06F1/3287 ,  H04W52/54 ,  Y02D10/128 ,  Y02D10/171

Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

Abstract translation: 提供了具有省电模式的媒体访问控制器。 特别地，本发明的媒体存取控制器通过在节电模式期间禁用应用于媒体访问控制器的所有块（包括CPU）的时钟来最小化功率损耗。 本发明的媒体存取控制器包括：一个节电主机，用于通过控制器中包含的各个处理器通过总线确保数据的稳定发送/接收; 唤醒定时器，注意节电模式已过期; 用于确定是否向锁相环提供电力的功率控制单元以及用于媒体访问控制器的时钟被应用和禁用的定时; 以及锁定时间寄存器，用于在锁相环的输出结束时存储锁定时间。 此外，提供了一种有效地将媒体访问控制器从活动模式改变到省电模式的方法，反之亦然。

公开(公告)号：US07180336B2

公开(公告)日：2007-02-20

申请号：US11109326

申请日：2005-04-19

Applicant: Yong-Mi Lee ,  Hae-Jin Song

Inventor： Yong-Mi Lee ,  Hae-Jin Song

IPC: G06F1/08 ,  H03K17/00

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: In a clock switching apparatus, a corresponding mask clock signal is generated for at least one of first and second clock signals. A mask clock signal has an interval of a predetermined logical level near the switching between the clock signals. Each mask clock signal is synchronized to the first and/or second clock signals. Such an interval in the mask clock signal prevents occurrence of glitches in an output clock signal that is switched between at least one mask clock signal and/or at least one clock signal.

Abstract translation: 在时钟切换装置中，对于第一和第二时钟信号中的至少一个产生相应的屏蔽时钟信号。 屏蔽时钟信号具有在时钟信号之间的切换附近的预定逻辑电平的间隔。 每个屏蔽时钟信号与第一和/或第二时钟信号同步。 屏蔽时钟信号中的这种间隔防止在至少一个屏蔽时钟信号和/或至少一个时钟信号之间切换的输出时钟信号中出现毛刺。

公开(公告)号：US07133944B2

公开(公告)日：2006-11-07

申请号：US10756974

申请日：2004-01-14

Applicant: Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

Inventor： Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

IPC: G06F13/00

CPC classification number: H04W52/287 ,  G06F1/3209 ,  G06F1/3237 ,  G06F1/3287 ,  H04W52/54 ,  Y02D10/128 ,  Y02D10/171

Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

公开(公告)号：US20070016812A1

公开(公告)日：2007-01-18

申请号：US11525389

申请日：2006-09-22

Applicant: Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

Inventor： Hae-Jin Song ,  Kab-Joo Lee ,  Yong-Mi Lee

IPC: G06F1/00

CPC classification number: H04W52/287 ,  G06F1/3209 ,  G06F1/3237 ,  G06F1/3287 ,  H04W52/54 ,  Y02D10/128 ,  Y02D10/171

Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.

Abstract translation: 提供了具有省电模式的媒体访问控制器。 特别地，本发明的媒体存取控制器通过在节电模式期间禁用应用于媒体访问控制器的所有块（包括CPU）的时钟来最小化功率损耗。 本发明的媒体存取控制器包括：一个节电主机，用于通过控制器中包含的各个处理器通过总线确保数据的稳定发送/接收; 唤醒定时器，注意节电模式已过期; 用于确定是否向锁相环提供电力的功率控制单元以及用于媒体访问控制器的时钟被应用和禁用的定时; 以及锁定时间寄存器，用于在锁相环的输出结束时存储锁定时间。 此外，提供了一种有效地将媒体访问控制器从活动模式改变到省电模式的方法，反之亦然。

公开(公告)号：US20050270073A1

公开(公告)日：2005-12-08

申请号：US11109326

申请日：2005-04-19

Applicant: Yong-mi Lee ,  Hae-Jin Song

Inventor： Yong-mi Lee ,  Hae-Jin Song

IPC: G06F1/08 ,  G06F1/12 ,  H03K3/00

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: In a clock switching apparatus, a corresponding mask clock signal is generated for at least one of first and second clock signals. A mask clock signal has an interval of a predetermined logical level near the switching between the clock signals. Each mask clock signal is synchronized to the first and/or second clock signals. Such an interval in the mask clock signal prevents occurrence of glitches in an output clock signal that is switched between at least one mask clock signal and/or at least one clock signal.

Abstract translation: 在时钟切换装置中，对于第一和第二时钟信号中的至少一个产生相应的屏蔽时钟信号。 屏蔽时钟信号具有在时钟信号之间的切换附近的预定逻辑电平的间隔。 每个屏蔽时钟信号与第一和/或第二时钟信号同步。 屏蔽时钟信号中的这种间隔防止在至少一个屏蔽时钟信号和/或至少一个时钟信号之间切换的输出时钟信号中发生毛刺。