公开(公告)号：US10372602B2

公开(公告)日：2019-08-06

申请号：US15545901

申请日：2015-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20180018258A1

公开(公告)日：2018-01-18

申请号：US15545901

申请日：2015-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/7203 ,  Y02D10/13

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US10997064B2

公开(公告)日：2021-05-04

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20190317891A1

公开(公告)日：2019-10-17

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0868 ,  G06F12/0804

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.