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    Systems and methods for streaming storage device content
    3.
    发明授权
    Systems and methods for streaming storage device content 有权

    公开(公告)号：US12050537B2

    公开(公告)日：2024-07-30

    申请号：US17856918

    申请日：2022-07-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Oscar P. Pinto

    IPC: G06F12/0868 ,  G06F9/30 ,  G06F12/02 ,  G06F30/331

    CPC classification number: G06F12/0868 ,  G06F9/30145 ,  G06F12/0246 ,  G06F30/331

    Abstract: A method of streaming between a storage device and a secondary device includes receiving, by the storage device, from the secondary device, a memory read request command including a memory address of the storage device corresponding to a stream identity, the stream identity being unique between the storage device and the secondary device; streaming, by the storage device, data between the storage device and the secondary device by transferring the data corresponding to the memory address of the storage device to the secondary device; determining, by the storage device, that the data requested by the secondary device in the memory read request command is transferred to the secondary device; and ending, by the storage device, the streaming between the storage device and the secondary device.

    CACHE MANAGEMENT USING SHARED CACHE LINE STORAGE
    4.
    发明公开
    CACHE MANAGEMENT USING SHARED CACHE LINE STORAGE 审中-公开

    公开(公告)号：US20240241830A1

    公开(公告)日：2024-07-18

    申请号：US18413211

    申请日：2024-01-16

    Applicant: Akeana, Inc.

    Inventor： Sanjay Patel ,  Yogesh Shamkant Thombre

    IPC: G06F12/0817 ,  G06F12/0868 ,  G06F12/0873

    CPC classification number: G06F12/0828 ,  G06F12/0868 ,  G06F12/0873

    Abstract: Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

    Memory data security
    9.
    发明授权
    Memory data security 有权

    公开(公告)号：US11928246B2

    公开(公告)日：2024-03-12

    申请号：US17346908

    申请日：2021-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Alberto Troia ,  Antonino Mondello

    IPC: H04L29/06 ,  G06F12/0868 ,  G06F12/0882 ,  G06F12/14 ,  G06F13/16 ,  G06F21/64 ,  G06F21/78

    CPC classification number: G06F21/64 ,  G06F12/0868 ,  G06F12/0882 ,  G06F12/1408 ,  G06F12/1441 ,  G06F13/1673 ,  G06F21/78 ,  G06F2212/1052

    Abstract: Content within a memory device (e.g., a DRAM) may be secured in a customizable manner. Data can be secured and the memory device performance by be dynamically defined. In some examples, setting a data security level for a group of memory cells of a memory device may be based, at least in part, on a security mode bit pattern (e.g., a flag, flags, or indicator) in metadata read from or written to the memory device. Some examples include comparing a first signature (e.g., a digital signature) in metadata to a second value (e.g., an expected digital signature) to validate the first value in the metadata. The first value and the second value can be based, at least in part, on the data security level. Some examples include performing a data transfer operation in response to validation of the first and/or second values.

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