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公开(公告)号：US5635950A
公开(公告)日：1997-06-03
申请号：US415668
申请日：1995-04-05
申请人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
发明人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
CPC分类号： G09G3/2011 , G09G3/2081 , G09G3/3688 , H04N3/127 , G09G2310/027 , G09G3/2014
摘要： In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to the digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.
摘要翻译： 在其中输入数字视频信号并且其中设置有多个并行信号电极的显示装置的驱动电路中，根据数字视频信号或两个相邻的数字视频信号输出具有不同电平的信号电压之一 所述信号电压同时输出。 或者，信号电压中的一个在一个输出周期的一部分中被提供给信号电极，并且另一个信号电压在输出周期的另一部分中被提供给信号电极。 根据数字视频信号适当地确定一个输出周期的两个部分的长度比，由此可以将对应于视频信号数据的任意电压施加到像素。
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公开(公告)号：US5686933A
公开(公告)日：1997-11-11
申请号：US316821
申请日：1994-10-03
申请人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
发明人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
CPC分类号： G09G3/2011 , G09G3/2081 , G09G3/3688 , H04N3/127 , G09G2310/027 , G09G3/2014
摘要： In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to a digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.
摘要翻译： 在其中输入数字视频信号并且其中设置有多个并行信号电极的显示装置的驱动电路中，根据数字视频信号或两个相邻的数字视频信号输出具有不同电平的信号电压之一 所述信号电压同时输出。 或者，信号电压中的一个在一个输出周期的一部分中被提供给信号电极，并且另一个信号电压在输出周期的另一部分中被提供给信号电极。 根据数字视频信号适当地确定一个输出周期的两个部分的长度比，由此可以对像素应用与视频信号数据相对应的任意电压。
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公开(公告)号：US5623278A
公开(公告)日：1997-04-22
申请号：US416645
申请日：1995-04-05
申请人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
发明人： Hisao Okada , Shigeyuki Uehira , Katumi Miki , Kuniaki Tanaka , Toshihiro Yanagi
CPC分类号： G09G3/2011 , G09G3/2081 , G09G3/3688 , H04N3/127 , G09G2310/027 , G09G3/2014
摘要： In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to a digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.
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公开(公告)号：US5245431A
公开(公告)日：1993-09-14
申请号：US742899
申请日：1991-08-08
申请人： Hisao Okada , Shigeyuki Uehira , Kuniaki Tanaka , Katumi Miki , Miki Fukuyama
发明人： Hisao Okada , Shigeyuki Uehira , Kuniaki Tanaka , Katumi Miki , Miki Fukuyama
IPC分类号： H04N5/10
CPC分类号： H04N5/10
摘要： In a synchronizing signal selection circuit, in response to the input of a vertical synchronizing signal extracted from a composite synchronizing signal, a control signal is generated. The control signal is in a predetermined state during a period which begins when a first predetermined time period has elapsed after the input of the vertical synchronizing signal, and which terminates when a second predetermined time period has elapsed after the input of the vertical synchronizing signal. The composite synchronizing signal is output when the control signal is in the predetermined state, and a horizontal synchronizing signal separated the composite synchronizing signal is output when the control signal is in a state other than the predetermined state.
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