公开(公告)号：US11169938B2

公开(公告)日：2021-11-09

申请号：US16673320

申请日：2019-11-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/362 ,  G06F13/42

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US11579803B2

公开(公告)日：2023-02-14

申请号：US17130363

申请日：2020-12-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

公开(公告)号：US20200065264A1

公开(公告)日：2020-02-27

申请号：US16673320

申请日：2019-11-04

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/362 ,  G06F9/50

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US11467764B2

公开(公告)日：2022-10-11

申请号：US17072038

申请日：2020-10-16

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F3/06

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

公开(公告)号：US20220027292A1

公开(公告)日：2022-01-27

申请号：US17498348

申请日：2021-10-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/362 ,  G06F13/42

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US20250094218A1

公开(公告)日：2025-03-20

申请号：US18963706

申请日：2024-11-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Bo Fang ,  Jiashu Lin ,  Hu Liu ,  Hou Fun Lam ,  Qiuyi Pan

IPC: G06F9/48 ,  G06F9/54

Abstract: This disclosure provides a scheduling apparatus and method, and a related device. The scheduling apparatus includes a dispatcher coupled to an execution apparatus. The dispatcher includes a plurality of first buffers, each of the plurality of first buffers is configured to cache target tasks of one task type, the target tasks include a thread subtask and a cache management operation task, and the cache management operation task indicates to perform a cache management operation on input data or output data of the thread subtask. The dispatcher is configured to: receive a plurality of first target tasks, and cache the plurality of first target tasks in the plurality of first buffers based on task types; and dispatch a plurality of second target tasks to the execution apparatus.

公开(公告)号：US11636052B2

公开(公告)日：2023-04-25

申请号：US17498348

申请日：2021-10-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/362 ,  G06F13/42

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

公开(公告)号：US20210109681A1

公开(公告)日：2021-04-15

申请号：US17130363

申请日：2020-12-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

公开(公告)号：US20210034284A1

公开(公告)日：2021-02-04

申请号：US17072038

申请日：2020-10-16

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Victor Gissin ,  Junying Li ,  Guanfeng Zhou ,  Jiashu Lin

IPC: G06F3/06

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.