STORAGE ARRAY AT LOW LEAKAGE CURRENT

    公开(公告)号:US20230054139A1

    公开(公告)日:2023-02-23

    申请号:US18048854

    申请日:2022-10-23

    Abstract: A storage array includes a read bit line, a ground, a read bit line switch of the read bit line, and a plurality of storage circuits. Each storage circuit includes a storage unit configured to store data and a read circuit configured to read data from the storage unit. A data input end of the read circuit is connected to a data output end of the storage unit, to read data from the storage circuit, and a data output end of the read circuit is connected to the read bit line, to output the read data to the read bit line. There is at least one PMOS transistor in an electric leakage path from a power supply to the read bit line in the read circuit, to suppress a leakage current in the read circuit.

    Mobile Terminal
    2.
    发明申请

    公开(公告)号:US20220006478A1

    公开(公告)日:2022-01-06

    申请号:US17294252

    申请日:2018-11-16

    Abstract: A mobile terminal, includes a housing, and a middle frame and a display that are disposed in the housing. The display is coupled to the middle frame. An accommodation space is formed between the display and the middle frame. In addition, the mobile terminal further includes a first magnet and a second magnet, and a part of the first magnet and a part of the second magnet are disposed in the accommodation space. The first magnet is disposed on a back facet of the display, the second magnet is disposed on the middle frame, and the first magnet and the second magnet are disposed face to face.

    Storage array having half schmitt inverter

    公开(公告)号:US12106802B2

    公开(公告)日:2024-10-01

    申请号:US18048854

    申请日:2022-10-23

    CPC classification number: G11C11/419 G11C11/412

    Abstract: A storage array includes a read bit line, a ground, a read bit line switch of the read bit line, and a plurality of storage circuits. Each storage circuit includes a storage unit configured to store data and a read circuit configured to read data from the storage unit. A data input end of the read circuit is connected to a data output end of the storage unit, to read data from the storage circuit, and a data output end of the read circuit is connected to the read bit line, to output the read data to the read bit line. There is at least one PMOS transistor in an electric leakage path from a power supply to the read bit line in the read circuit, to suppress a leakage current in the read circuit.

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