中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.008 seconds)

    Computing system embodying flexible subroutine capabilities
    2.
    发明授权
    Computing system embodying flexible subroutine capabilities 失效
    体现灵活子程序功能的计算系统

    公开(公告)号：US3366929A

    公开(公告)日：1968-01-30

    申请号：US42234364

    申请日：1964-12-30

    Applicant: IBM

    Inventor： MULLERY ALVIN P ,  RIEKERT ROBERT H ,  SCHAUER RALPH F

    IPC: G06F9/42

    CPC classification number: G06F9/4426

    Abstract: 1,091,937. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 3, 1965 [Dec. 30, 1964], No. 51340/65. Addition to 1,007,415. Heading G4A. In a digital computer, means are provided for storing the address of a parameter relating to a sub-routine of a nest of sub-routines, in an address characteristic of the position of the sub-routine in the nest and the position of the parameter with respect to other parameters in the sub-routine call instruction. A multi-character instruction, placed in an instruction register and normally decoded character by character selected under control of a ring, may contain a sub-routine call consisting of, in order, a special start character (º), a two-character name which is the beginning address of the sub-routine, followed by one or more two-character parameters for use in the sub-routine each preceded by a special character (,), the sub-routine call ending with a special end character (Â). Each parameter is either the address of an operand, or a special character (call " par ") followed by a number. The instruction decoder recognizes the special characters and initiates gated chains of singleshots to control operations relating to calling sub-routines. Sub-routines may call other subroutines, forming a hierarchy of sub-routine levels limited only by storage constraints. As a sub-routine call is decoded, its parameters, if they are operand addresses, are stored in addresses specified by the concatenation of a level counter specifying the sub-routine level in the hierarchy and a parameter counter specifying the ordinal number of the parameter in the call. If a parameter is of the form " par n " n is placed in the parameter counter the previous count being saved in a register and the level counter is temporarily decremented to reach the next higher level, the operand address corresponding to " par n " then being accessed at the address specified by the counters and, after restoration of the counters, stored under their control. When the end character of the call is reached, the current instruction address, from an instruction address register and the current ring position are placed in a push-down store as the return address, together with the contents of a sub-routine end address register which, if the call is within another sub-routine, will be holding the end address of that subroutine. Then the sub-routine beginning address moved from the call to a sub-routine address register is used to access the sub-routine and pass it to the instruction register instruction by instruction under control of the instruction address register. The sub-routine starts with its own end address which is stored in the subroutine end address register and compared with the instruction address register during subroutine execution to indicate when the subroutine has been completed. (Alternatively this can be done using a special mark at the end of the sub-routine). After execution, the pushdown store permits return to the next higher level by loading the instruction address register and the sub-routine end address register and setting the instruction register ring, the level counter also being decremented. Sub-routines contain dummy parameters to be replaced by parameters specified in the call, the dummy parameters being of the form " par n " (see above), so when the sub-routine is executed, the corresponding operand address is obtained as in the decoding of calls (see above). A parameter may be an arithmetic expression or a sub-routine call, the latter allowing recursive definition of sub-routines. A sub-routine may be used in a loop which is iterated until a specified condition is satisfied. Sub-routines can be stored in read-write storage or read-only (e.g. a microprogramming read-only store). The invention is described as an addition to the system of Specification 1,007,415. Reference has been directed by the Comptroller to Specification 997,104.

    Arrangement for automatically selecting units for task executions in data processing systems
    3.
    发明授权
    Arrangement for automatically selecting units for task executions in data processing systems 失效
    自动选择数据处理系统中任务执行单位的安排

    公开(公告)号：US3593300A

    公开(公告)日：1971-07-13

    申请号：US3593300D

    申请日：1967-11-13

    Applicant: IBM

    Inventor： DRISCOLL GRAHAM C JR ,  MULLERY ALVIN P

    IPC: G06F9/46 ,  G06F15/16 ,  G06F15/20

    CPC classification number: G06F9/468

    Abstract: An arrangement in a data processing system which comprises a multiplicity of active components, or entities, such as processors, I/O devices, channels, etc., that have overlapping but not necessarily identical capabilities wherein there is enabled an automatic selection of an active entity for the execution of a chosen task by the use of hardware. In this regard, each active entity has associated therewith a capability factor, or vector, wherein each discrete position of the vector is related to a particular capability of the component, each capability being assigned an individual power weight. It is stipulated that a requirement vector be given as part of the specification of each task, the requirement vector being the same length as the capability vector, registered positions in the requirement and capability vectors pertaining to the same capability. In order to enable the selection of one of a number of active entities capable of executing a given task, each active entity is provided with a power index contained in a power vector. All of the power vectors respectively have the same number of positions, the latter number being at least equal to the greatest number of capabilities possessed by any entity in the system. When a plurality of active entities are available at any given time to execute a task offered for execution, an automatic selection is made to provide, for the execution of the task, that available properly capable active entity which has the lowest power index, the power index being the sum of the weights of the capabilities of a given active entity as set forth in its power vector.

    Program scheduler for processing systems
    5.
    发明授权
    Program scheduler for processing systems 失效
    程序处理系统的程序设计

    公开(公告)号：US3648253A

    公开(公告)日：1972-03-07

    申请号：US3648253D

    申请日：1969-12-10

    Applicant: IBM ,  BURROUGHS CORP

    Inventor： MULLERY ALVIN P ,  ZURCHER FRANK W JR

    IPC: G06F9/48 ,  G06F9/18

    CPC classification number: G06F9/4825 ,  G06F9/4887

    Abstract: A program scheduler is provided for use with a multiprocessor system or its equivalent, such as a multiprogrammed processor unit, and the program scheduler receives tasks to be executed, schedules them for assignment, allots a task to each processor and interrupts the processors to assign new tasks. The program scheduler includes a plurality of buckets or tables where task words are stored, and associated with each task word is a Te field which specifies the estimated processor time required to complete the task and a Td field which indicates the time remaining before the task must be completed. The ratio Te/Td provides an indication of the need of each task word for processor service since the need for such service becomes more urgent as the ratio approaches 1. A scheduling algorithm periodically recalculates the service ratio and shifts tasks, if need be, from one table to another whereby tasks with a similar service ratio are stored in a common table. Task words within a given table are divided into classes according to the length of time a task has not received service. An allocation algorithm allots tasks to processors from the older classes first and proceeds in sequence through the various classes to the latest classes. Both the scheduling algorithm and the allocation algorithm service all tables in the program scheduler, but the tables with higher service ratios are serviced more often by each algorithm than tables with lower service ratios. When many task words are awaiting processor service, a given task word receives processor service at a rather low frequency when it has a small service ratio, but it receives processor service at a relatively high frequency as its service ratio approaches 1.

    Abstract translation: 提供了一种与多处理器系统或其等同物（例如多程序处理器单元）一起使用的程序调度器，并且程序调度器接收要执行的任务，调度它们进行分配，将任务分配给每个处理器并中断处理器以分配新的 任务。 程序调度器包括多个桶或表，其中存储任务字，并且与每个任务字相关联的是指定完成任务所需的估计处理器时间的Te字段和指示在任务必须之前剩余的时间的Td字段 完成 比率Te / T d提供了处理器服务的每个任务字的需要的指示，因为当比率接近1时，对这种服务的需求变得更加迫切。调度算法周期性地重新计算服务比例并且移动任务，如果需要的话， 从一个表到另一个表，其中具有相似服务比率的任务存储在公用表中。 给定表中的任务字根据任务未接收到服务的时间长度划分为类。 分配算法首先将任务从旧类分配给处理器，并通过各种类顺序进行到最新的类。 调度算法和分配算法都为程序调度程序中的所有表提供服务，但是具有较高服务比率的表比每个算法更频繁地服务于具有较低服务比率的表。 当许多任务字等待处理器服务时，给定的任务字在具有小的服务比率时以相当低的频率接收处理器服务，但是当服务比接近1时，它以相对高的频率接收处理器服务。

    Computer instruction sequencing and control system
    7.
    发明授权
    Computer instruction sequencing and control system 失效
    计算机指令排序和控制系统

    公开(公告)号：US3293616A

    公开(公告)日：1966-12-20

    申请号：US29260663

    申请日：1963-07-03

    Applicant: IBM

    Inventor： MULLERY ALVIN P ,  SCHAUER RALPH F

    IPC: G06F9/40 ,  G06F15/78

    CPC classification number: G06F15/78 ,  G06F9/4425

    Abstract: 1,007,415. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 24, 1964 [July 3, 1963], No. 26047/64. Heading G4A. In a digital computer an instruction is processed by comparing two or more operators therein to determine their relative priority, the operands associated with the operator of higher or highest priority being operated on in accordance with said operator, the operators and operands of lower priority being stored together in a single store until required. The invention simplifies programming by allowing the computer to accept an instruction such as in this form. The computer performs the operations in such an instruction according to the priority order specified by the intrinsic priorities of the operations as modified by the parentheses. The general procedure is to scan the characters in the instruction in turn, comparing each operator (e.g. +, *) with the next and performing the first if of higher or equal priority with respect to the second, but storing the first operator along with its subject (e.g. A is the subject of the first + above) for action later if the first operator is of lower priority than the second. If the first operator is thus stored, the second is compared with the third, to see if it should be performed immediately or stored, and so on. However, if an opening parenthesis is encountered, it, its location and certain data about the state of the circuitry (see below) are stored, and the operators following the opening parenthesis compared in pairs etc. as above, until the corresponding closing parenthesis is encountered when any operator within the parentheses remaining unperformed is performed. Then the operator preceding the opening parenthesis is compared with that following the closing parenthesis to determine priority as before. Obviously nested sets of parentheses can be dealt with in this way. The procedure is such that operators stored for action later are withdrawn for performance as soon as performance becomes possible. Recursive instructions in which a particular mathematical operation is iterated until a specified condition is met can be dealt with using an " until " symbol. The particular embodiment can only deal with the operations of +, -, * (i.e. multiply, / (i.e. divide), = = (i.e. compare) and # (i.e. transfer to memory location, but the principles of the invention could be applied to other operations and some examples are mentioned at the end of the Specification. No details are given as to how any of the operations themselves are performed. The hardware includes the following units: (a) instruction push-down store IPDS, used for storing in connection with operations to be deferred, and which may be part of (b); (b) main memory; (c) instruction register IR (with a control ring to select a character therein); (d) IR decoder for recognizing characters, with outputs as in Fig. 2a (top left), the top output (" address ") being marked when the character received from the IR is the address (or rather half of the address) of an operand, and the fourth output from the top being concerned with a marker character used at the beginnings and ends of instructions; (e) IR word address register, specifying the main memory address of the word in the IR; (f) operator register OR; (g) OR decoder; (h) subject register (with control ring); (i) subject address register; (j) object register (with control ring); (k) object address register; (1) parenthesis control register, consisting of six latches as follows: (i) "conditional do " latch, set when a + or - is stored in the IPDS to indicate that if at a later time another + or - is reached then this preceding + or - in the IPDS can be performed, (ii) " do " latch, set when a *, / or = immediately precedes a left parenthesis, (iii) " may do " latch, set when a + or - immediately precedes a left parenthesis, (iv) three IDR latches settable to indicate types of left parenthesis encountered, mainly for use in connection with " until "-type instructions, and in which 010 means the left parenthesis follows an " until " symbol which has a parenthetical statement as its subject, 001 means the left parenthesis follows an " until " symbol which does not have a parenthetical statement as its subject, and 100 means the left parenthesis does not follow an " until " symbol; (m) a right parenthesis latch, set on detection of same. When a left parenthesis is stored in the IPDS the address of its instruction word, the position of the parenthesis in the word and the contents of the parenthesis control register are stored with it, all these items first being assembled in the object register. Figs. 2a, 2b, 2c show the sequences of actions performed on encountering various characters in the IR.

Patent Agency Ranking