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    Computing system embodying flexible subroutine capabilities
    1.
    发明授权
    Computing system embodying flexible subroutine capabilities 失效
    体现灵活子程序功能的计算系统

    公开(公告)号：US3366929A

    公开(公告)日：1968-01-30

    申请号：US42234364

    申请日：1964-12-30

    Applicant: IBM

    Inventor： MULLERY ALVIN P ,  RIEKERT ROBERT H ,  SCHAUER RALPH F

    IPC: G06F9/42

    CPC classification number: G06F9/4426

    Abstract: 1,091,937. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 3, 1965 [Dec. 30, 1964], No. 51340/65. Addition to 1,007,415. Heading G4A. In a digital computer, means are provided for storing the address of a parameter relating to a sub-routine of a nest of sub-routines, in an address characteristic of the position of the sub-routine in the nest and the position of the parameter with respect to other parameters in the sub-routine call instruction. A multi-character instruction, placed in an instruction register and normally decoded character by character selected under control of a ring, may contain a sub-routine call consisting of, in order, a special start character (º), a two-character name which is the beginning address of the sub-routine, followed by one or more two-character parameters for use in the sub-routine each preceded by a special character (,), the sub-routine call ending with a special end character (Â). Each parameter is either the address of an operand, or a special character (call " par ") followed by a number. The instruction decoder recognizes the special characters and initiates gated chains of singleshots to control operations relating to calling sub-routines. Sub-routines may call other subroutines, forming a hierarchy of sub-routine levels limited only by storage constraints. As a sub-routine call is decoded, its parameters, if they are operand addresses, are stored in addresses specified by the concatenation of a level counter specifying the sub-routine level in the hierarchy and a parameter counter specifying the ordinal number of the parameter in the call. If a parameter is of the form " par n " n is placed in the parameter counter the previous count being saved in a register and the level counter is temporarily decremented to reach the next higher level, the operand address corresponding to " par n " then being accessed at the address specified by the counters and, after restoration of the counters, stored under their control. When the end character of the call is reached, the current instruction address, from an instruction address register and the current ring position are placed in a push-down store as the return address, together with the contents of a sub-routine end address register which, if the call is within another sub-routine, will be holding the end address of that subroutine. Then the sub-routine beginning address moved from the call to a sub-routine address register is used to access the sub-routine and pass it to the instruction register instruction by instruction under control of the instruction address register. The sub-routine starts with its own end address which is stored in the subroutine end address register and compared with the instruction address register during subroutine execution to indicate when the subroutine has been completed. (Alternatively this can be done using a special mark at the end of the sub-routine). After execution, the pushdown store permits return to the next higher level by loading the instruction address register and the sub-routine end address register and setting the instruction register ring, the level counter also being decremented. Sub-routines contain dummy parameters to be replaced by parameters specified in the call, the dummy parameters being of the form " par n " (see above), so when the sub-routine is executed, the corresponding operand address is obtained as in the decoding of calls (see above). A parameter may be an arithmetic expression or a sub-routine call, the latter allowing recursive definition of sub-routines. A sub-routine may be used in a loop which is iterated until a specified condition is satisfied. Sub-routines can be stored in read-write storage or read-only (e.g. a microprogramming read-only store). The invention is described as an addition to the system of Specification 1,007,415. Reference has been directed by the Comptroller to Specification 997,104.

    Computer instruction sequencing and control system
    2.
    发明授权
    Computer instruction sequencing and control system 失效
    计算机指令排序和控制系统

    公开(公告)号：US3293616A

    公开(公告)日：1966-12-20

    申请号：US29260663

    申请日：1963-07-03

    Applicant: IBM

    Inventor： MULLERY ALVIN P ,  SCHAUER RALPH F

    IPC: G06F9/40 ,  G06F15/78

    CPC classification number: G06F15/78 ,  G06F9/4425

    Abstract: 1,007,415. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 24, 1964 [July 3, 1963], No. 26047/64. Heading G4A. In a digital computer an instruction is processed by comparing two or more operators therein to determine their relative priority, the operands associated with the operator of higher or highest priority being operated on in accordance with said operator, the operators and operands of lower priority being stored together in a single store until required. The invention simplifies programming by allowing the computer to accept an instruction such as in this form. The computer performs the operations in such an instruction according to the priority order specified by the intrinsic priorities of the operations as modified by the parentheses. The general procedure is to scan the characters in the instruction in turn, comparing each operator (e.g. +, *) with the next and performing the first if of higher or equal priority with respect to the second, but storing the first operator along with its subject (e.g. A is the subject of the first + above) for action later if the first operator is of lower priority than the second. If the first operator is thus stored, the second is compared with the third, to see if it should be performed immediately or stored, and so on. However, if an opening parenthesis is encountered, it, its location and certain data about the state of the circuitry (see below) are stored, and the operators following the opening parenthesis compared in pairs etc. as above, until the corresponding closing parenthesis is encountered when any operator within the parentheses remaining unperformed is performed. Then the operator preceding the opening parenthesis is compared with that following the closing parenthesis to determine priority as before. Obviously nested sets of parentheses can be dealt with in this way. The procedure is such that operators stored for action later are withdrawn for performance as soon as performance becomes possible. Recursive instructions in which a particular mathematical operation is iterated until a specified condition is met can be dealt with using an " until " symbol. The particular embodiment can only deal with the operations of +, -, * (i.e. multiply, / (i.e. divide), = = (i.e. compare) and # (i.e. transfer to memory location, but the principles of the invention could be applied to other operations and some examples are mentioned at the end of the Specification. No details are given as to how any of the operations themselves are performed. The hardware includes the following units: (a) instruction push-down store IPDS, used for storing in connection with operations to be deferred, and which may be part of (b); (b) main memory; (c) instruction register IR (with a control ring to select a character therein); (d) IR decoder for recognizing characters, with outputs as in Fig. 2a (top left), the top output (" address ") being marked when the character received from the IR is the address (or rather half of the address) of an operand, and the fourth output from the top being concerned with a marker character used at the beginnings and ends of instructions; (e) IR word address register, specifying the main memory address of the word in the IR; (f) operator register OR; (g) OR decoder; (h) subject register (with control ring); (i) subject address register; (j) object register (with control ring); (k) object address register; (1) parenthesis control register, consisting of six latches as follows: (i) "conditional do " latch, set when a + or - is stored in the IPDS to indicate that if at a later time another + or - is reached then this preceding + or - in the IPDS can be performed, (ii) " do " latch, set when a *, / or = immediately precedes a left parenthesis, (iii) " may do " latch, set when a + or - immediately precedes a left parenthesis, (iv) three IDR latches settable to indicate types of left parenthesis encountered, mainly for use in connection with " until "-type instructions, and in which 010 means the left parenthesis follows an " until " symbol which has a parenthetical statement as its subject, 001 means the left parenthesis follows an " until " symbol which does not have a parenthetical statement as its subject, and 100 means the left parenthesis does not follow an " until " symbol; (m) a right parenthesis latch, set on detection of same. When a left parenthesis is stored in the IPDS the address of its instruction word, the position of the parenthesis in the word and the contents of the parenthesis control register are stored with it, all these items first being assembled in the object register. Figs. 2a, 2b, 2c show the sequences of actions performed on encountering various characters in the IR.

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