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    Arrangement for automatically selecting units for task executions in data processing systems
    1.
    发明授权
    Arrangement for automatically selecting units for task executions in data processing systems 失效
    自动选择数据处理系统中任务执行单位的安排

    公开(公告)号：US3593300A

    公开(公告)日：1971-07-13

    申请号：US3593300D

    申请日：1967-11-13

    Applicant: IBM

    Inventor： DRISCOLL GRAHAM C JR ,  MULLERY ALVIN P

    IPC: G06F9/46 ,  G06F15/16 ,  G06F15/20

    CPC classification number: G06F9/468

    Abstract: An arrangement in a data processing system which comprises a multiplicity of active components, or entities, such as processors, I/O devices, channels, etc., that have overlapping but not necessarily identical capabilities wherein there is enabled an automatic selection of an active entity for the execution of a chosen task by the use of hardware. In this regard, each active entity has associated therewith a capability factor, or vector, wherein each discrete position of the vector is related to a particular capability of the component, each capability being assigned an individual power weight. It is stipulated that a requirement vector be given as part of the specification of each task, the requirement vector being the same length as the capability vector, registered positions in the requirement and capability vectors pertaining to the same capability. In order to enable the selection of one of a number of active entities capable of executing a given task, each active entity is provided with a power index contained in a power vector. All of the power vectors respectively have the same number of positions, the latter number being at least equal to the greatest number of capabilities possessed by any entity in the system. When a plurality of active entities are available at any given time to execute a task offered for execution, an automatic selection is made to provide, for the execution of the task, that available properly capable active entity which has the lowest power index, the power index being the sum of the weights of the capabilities of a given active entity as set forth in its power vector.

    Processor to processor communication in a multiprocessor computer system
    3.
    发明授权
    Processor to processor communication in a multiprocessor computer system 失效
    处理器在多处理器计算机系统中的通信处理器

    公开(公告)号：US3566363A

    公开(公告)日：1971-02-23

    申请号：US3566363D

    申请日：1968-07-11

    Applicant: IBM

    Inventor： DRISCOLL GRAHAM C JR

    IPC: G06F13/16 ,  G06F13/36 ,  G06F15/167 ,  G06F15/16

    CPC classification number: G06F13/1663 ,  G06F13/36 ,  G06F15/167

    Abstract: IN A MULTIPROCESSOR COMPUTER SYSTEM, A MECHANISM IS PROVIDED ALLOWING INDIVIDUAL PROCESSOR UNITS TO COMMUNICATE WITH EACH OTHER VIA THE EXISTING STORAGE BUS MECHANISM. HARDWARE AND CONTROLS ARE PROVIDED WITHIN THE INDIVIDUAL PROCESSORS, THE BUSSING MECHANISM AND WITHIN THE STORAGE MODULES WHEREBY A GIVEN PROCESSOR MAY SEND A MESSAGE OVER THE STORAGE BUS TO THE STORAGE MODULE AND THE STORAGE MODULE CONTROLS WILL INITIATE COMMUNICATION WITH THE INDICATED PROCESSOR UNIT UPON THE RECEIPT OF SUCH A MESSAGE.

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