公开(公告)号：US20160126109A1

公开(公告)日：2016-05-05

申请号：US14934111

申请日：2015-11-05

Applicant: IMEC VZW

Inventor： Jianwu Sun ,  Roger Loo

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/161 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/32055 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.

Abstract translation: 一种用于制造在硅基衬底上的锗通道材料的晶体管器件的方法，所述方法包括提供浅沟槽隔离（STI）衬底，所述浅沟槽隔离（STI）衬底包括嵌入在STI电介质结构中的硅突起，并且部分地使所述硅突起凹陷， 在相邻的STI结构之间的沟槽，并且在凹入突起的上表面处提供V形槽。 该方法还包括在沟槽中生长Si1-xGex SRB层，并在Si1-xGex SRB层上生长基于锗的沟道层。 在该实施例中，Si1-xGex SRB层包含在20％至99％的范围内的锗含量x，并且SRB层具有小于400nm的厚度。 本公开还涉及相关联的晶体管器件。

公开(公告)号：US09640411B2

公开(公告)日：2017-05-02

申请号：US14934111

申请日：2015-11-05

Applicant: IMEC VZW

Inventor： Jianwu Sun ,  Roger Loo

IPC: H01L29/06 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/161 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/32055 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si1-xGex SRB layer in the trenches, and growing a germanium based channel layer on the Si1-xGex SRB layer. In this example, the Si1-xGex SRB layer comprises a germanium content x that is within the range of 20% to 99%, and the SRB layer has a thickness less than 400 nm. The present disclosure also relates to an associated transistor device.