公开(公告)号：US12112946B2

公开(公告)日：2024-10-08

申请号：US17677005

申请日：2022-02-22

Applicant: IMEC VZW

Inventor： Yuanyuan Shi ,  Benjamin Groven ,  Matty Caymax

IPC: H01L21/02 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L21/0262 ,  H01L21/02568 ,  H01L21/02598 ,  H01L21/02645 ,  H01L21/465 ,  H01L29/66969 ,  H01L21/0242 ,  H01L29/24

Abstract: A method for providing a film of one or more monolayers of transition metal dichalcogenides on a substrate is disclosed. The method includes providing a substrate; depositing at least one monolayer of the transition metal dichalcogenides on the substrate; and selectively removing superficial islands on top of the at least one monolayer by thermal etching.

公开(公告)号：US20240249939A1

公开(公告)日：2024-07-25

申请号：US18566563

申请日：2021-06-03

Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Inventor： Reza SOLEIMAN ZADEH ARDEBILI ,  Mehdi NAAMOUN ,  Elison de Nazareth MATIOLI

IPC: H01L21/02 ,  C01B32/25 ,  C23C16/27

CPC classification number: H01L21/02645 ,  C01B32/25 ,  C23C16/27 ,  H01L21/02389 ,  H01L21/02527 ,  C01P2002/82 ,  C01P2002/85 ,  C01P2004/03

Abstract: The present invention concerns a diamond device or structure comprising at least one supporting layer or material including at least one or a plurality of support structures inside the at least one supporting layer or material; a plurality of recesses defined by the at least one or the plurality of support structures; and at least one diamond micro-seed and a plurality of diamond nano-seeds located in each recess or in the plurality of recesses.

公开(公告)号：US20240141552A1

公开(公告)日：2024-05-02

申请号：US18279023

申请日：2022-03-04

Applicant: SHIN-ETSU CHEMICAL CO., LTD. ,  SHIN-ETSU HANDOTAI CO., LTD.

Inventor： Yoshihiro KUBOTA ,  Ippei KUBONO

IPC: C30B25/18 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C30B29/40 ,  C30B31/22 ,  H01L21/02 ,  H01L29/20

CPC classification number: C30B25/186 ,  C23C16/301 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/50 ,  C30B29/403 ,  C30B31/22 ,  H01L21/02645 ,  H01L29/2003

Abstract: A seed substrate for epitaxial growth has a support substrate, a planarizing layer of 0.5 to 3 μm provided on the top surface of the support substrate, and a seed crystal layer provided on the top surface of the planarizing layer. The support substrate includes a core of group III nitride polycrystalline ceramics and a 0.05 to 1.5 μm encapsulating layer that encapsulates the core. The seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 μm of the surface layer of Si single crystal with oxidation-induced stacking faults (OSF) of 10 defects/cm2 or less. High-quality, inexpensive seed substrates with few crystal defects for epitaxial growth of epitaxial substrates and solid substrates of group III nitrides such as AlN, AlxGa1-xN (0

公开(公告)号：US11961737B2

公开(公告)日：2024-04-16

申请号：US17447861

申请日：2021-09-16

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Zhenyu Liu

IPC: H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02645 ,  H01L21/0262 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate including a base and a plurality of fins discretely formed over the base. Each fin is made of a material including a first atom and contains openings therein. The semiconductor structure also includes a source-drain doped layer located in each opening and including a seed layer on a surface of an inner wall of the opening and a body layer on a surface of the seed layer. A material of the seed layer includes the first atom, a second atom, and a third atom. A material of the body layer includes the first atom and the second atom.

公开(公告)号：US11862512B2

公开(公告)日：2024-01-02

申请号：US17185978

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L23/053 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/538 ,  H01L21/78 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/76807 ,  H01L21/02645 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/5329 ,  H01L23/5384 ,  H01L24/32 ,  H01L2221/1015 ,  H01L2224/0231 ,  H01L2224/32225 ,  H01L2924/14

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US20190206679A1

公开(公告)日：2019-07-04

申请号：US16234087

申请日：2018-12-27

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Kiyohiko MAEDA ,  Masato TERASAKI ,  Yasuhiro MEGAWA ,  Takahiro MIYAKURA ,  Akito HIRANO ,  Takashi NAKAGAWA

IPC: H01L21/02 ,  C23C16/46 ,  C23C16/455 ,  C23C16/24 ,  C23C16/06

CPC classification number: H01L21/02667 ,  C23C16/06 ,  C23C16/24 ,  C23C16/455 ,  C23C16/46 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02645

Abstract: There is provided a technique that includes: (a) forming a silicon germanium film in an amorphous state so as to embed an inside of a recess formed on a surface of a substrate, by supplying a first silicon-containing gas and a germanium-containing gas to the substrate at a first temperature; (b) raising a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature; and (c) forming a silicon film on the silicon germanium film by supplying a second silicon-containing gas to the substrate at the second temperature, wherein in (c), the silicon germanium film as a base of the silicon film is crystallized while the silicon film is formed.

公开(公告)号：US20190013393A1

公开(公告)日：2019-01-10

申请号：US16129329

申请日：2018-09-12

Applicant: International Business Machines Corporation

Inventor： Sanghoon Lee ,  Effendi Leobandung ,  Renee Mo ,  Brent A. Wacaser

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/265 ,  H01L29/786 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L29/66522 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/26546 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30612 ,  H01L21/30617 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/7624 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

公开(公告)号：US20180358226A1

公开(公告)日：2018-12-13

申请号：US15573772

申请日：2016-05-13

Applicant: STC.UNM

Inventor： Seung-Chang Lee ,  Steven R.J. Brueck

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02664 ,  B81C1/00111 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/2855 ,  H01L21/30608 ,  H01L21/31116 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

公开(公告)号：US20180240893A9

公开(公告)日：2018-08-23

申请号：US15792449

申请日：2017-10-24

Applicant: Applied Materials, Inc.

Inventor： Matthias BAUER ,  Hans-Joachim L. GOSSMANN ,  Benjamin COLOMBEAU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/26 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/306 ,  H01L29/167 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/26 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/20 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

公开(公告)号：US10037916B2

公开(公告)日：2018-07-31

申请号：US15464028

申请日：2017-03-20

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/161 ,  H01L21/84 ,  H01L21/308 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/36 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.