公开(公告)号：US10607896B2

公开(公告)日：2020-03-31

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US20170330801A1

公开(公告)日：2017-11-16

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823857 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66545

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.