公开(公告)号：US09287273B2

公开(公告)日：2016-03-15

申请号：US14733880

申请日：2015-06-08

申请人： IMEC VZW

发明人： Lars-Ake Ragnarsson ,  Tom Schram ,  Hendrik F. W. Dekkers ,  Soon Aik Chew

IPC分类号： H01L21/8234 ,  H01L27/112

CPC分类号： H01L27/112 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/82345 ,  H01L21/823842

摘要： The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

摘要翻译： 所公开的技术通常涉及包括晶体管的半导体器件，更具体地涉及包括具有不同有效功函的栅叠层的晶体管的半导体器件，以及制造这种器件的方法。 在一个方面，制造半导体的方法包括在衬底中提供至少两个沟道区，并在衬底上提供介电层。 该方法还包括通过在电介质层中设置开口来形成多个栅极区域。 该方法还包括在开口中提供栅极电介质层，并且在每个栅极区域的栅极电介质层上提供沿着不同栅极区域具有不同厚度的势垒层叠层。

公开(公告)号：US10607896B2

公开(公告)日：2020-03-31

申请号：US15591944

申请日：2017-05-10

申请人： IMEC VZW

发明人： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02

摘要： The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US09892923B2

公开(公告)日：2018-02-13

申请号：US14757811

申请日：2015-12-22

申请人： IMEC VZW

发明人： Hendrik F. W. Dekkers ,  Lars-Ake Ragnarsson ,  Tom Schram

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

摘要： The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.

公开(公告)号：US20170330801A1

公开(公告)日：2017-11-16

申请号：US15591944

申请日：2017-05-10

申请人： IMEC VZW

发明人： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/823857 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66545

摘要： The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US20230189497A1

公开(公告)日：2023-06-15

申请号：US18064133

申请日：2022-12-09

申请人： IMEC VZW

发明人： Cedric Huyghebaert ,  Tom Schram ,  Iuliana Radu

IPC分类号： H10B10/00 ,  G11C11/419

CPC分类号： H10B10/125 ,  G11C11/419

摘要： The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.

公开(公告)号：US20150357244A1

公开(公告)日：2015-12-10

申请号：US14733880

申请日：2015-06-08

申请人： IMEC VZW

发明人： Lars-Ake Ragnarsson ,  Tom Schram ,  Hendrik F.W. Dekkers ,  Soon Aik Chew

IPC分类号： H01L21/8234 ,  H01L21/285 ,  H01L21/28

CPC分类号： H01L27/112 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/82345 ,  H01L21/823842

摘要： The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

摘要翻译： 所公开的技术通常涉及包括晶体管的半导体器件，更具体地涉及包括具有不同有效功函的栅叠层的晶体管的半导体器件，以及制造这种器件的方法。 在一个方面，制造半导体的方法包括在衬底中提供至少两个沟道区，并在衬底上提供介电层。 该方法还包括通过在电介质层中设置开口来形成多个栅极区域。 该方法还包括在开口中提供栅极电介质层，并且在每个栅极区域的栅极电介质层上提供沿着不同栅极区域具有不同厚度的势垒层叠层。