公开(公告)号：US20240363755A1

公开(公告)日：2024-10-31

申请号：US18531497

申请日：2023-12-06

申请人： Adeia Semiconductor Solutions LLC

发明人： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

公开(公告)号：US20240332188A1

公开(公告)日：2024-10-03

申请号：US18742102

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gerben DOORNBOS

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/481 ,  H01L27/0924 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2027/11881

摘要： A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate.

公开(公告)号：US12107133B2

公开(公告)日：2024-10-01

申请号：US17379265

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC分类号： H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/7851

摘要： FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US12107085B2

公开(公告)日：2024-10-01

申请号：US18219374

申请日：2023-07-07

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

摘要： Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20240313116A1

公开(公告)日：2024-09-19

申请号：US18670123

申请日：2024-05-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2029/7858

摘要： A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US12027608B2

公开(公告)日：2024-07-02

申请号：US17325622

申请日：2021-05-20

申请人： DO NOT USE—Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Ming-Ching Chang

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

公开(公告)号：US20240215267A1

公开(公告)日：2024-06-27

申请号：US18596623

申请日：2024-03-06

申请人： Monolithic 3D Inc.

发明人： Deepak C. Sekar ,  Zvi Or-Bach

IPC分类号： H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

摘要： A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

公开(公告)号：USRE49988E1

公开(公告)日：2024-05-28

申请号：US17569902

申请日：2022-01-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Myung-Gil Kang ,  Sung-Bong Kim ,  Chang-Woo Oh ,  Dong-Won Kim

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/775 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

摘要： An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

公开(公告)号：US20240170340A1

公开(公告)日：2024-05-23

申请号：US18425390

申请日：2024-01-29

申请人： Samsung Electronics Co., Ltd.

发明人： Juyoun KIM

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

公开(公告)号：US11955517B2

公开(公告)日：2024-04-09

申请号：US17098412

申请日：2020-11-15

申请人： Samsung Electronics Co., Ltd.

发明人： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC分类号： H01L21/8234 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775

CPC分类号： H01L29/0692 ,  B82Y10/00 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/775

摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.