公开(公告)号：US11257764B2

公开(公告)日：2022-02-22

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/50 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

公开(公告)号：US12154830B2

公开(公告)日：2024-11-26

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US20200373242A1

公开(公告)日：2020-11-26

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/50 ,  H01L21/768

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.