公开(公告)号：US10461781B2

公开(公告)日：2019-10-29

申请号：US16011483

申请日：2018-06-18

Applicant: INPHI CORPORATION

Inventor： Benjamin Smith ,  Arash Farhoodfar ,  Stewart Crozier ,  Frank R. Kschischang ,  Andrew Hunt

IPC: H04L25/34 ,  H03M13/29 ,  H04L1/00 ,  H04L25/49 ,  H04L27/04 ,  H03M13/15

Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

公开(公告)号：US10601449B2

公开(公告)日：2020-03-24

申请号：US16575236

申请日：2019-09-18

Applicant: INPHI CORPORATION

Inventor： Benjamin Smith ,  Arash Farhoodfar ,  Stewart Crozier ,  Frank R. Kschischang ,  Andrew Hunt

IPC: H04L25/34 ,  H03M13/29 ,  H04L1/00 ,  H04L25/49 ,  H04L27/04 ,  H03M13/15

Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

公开(公告)号：US10033410B2

公开(公告)日：2018-07-24

申请号：US15206011

申请日：2016-07-08

Applicant: INPHI CORPORATION

Inventor： Benjamin Smith ,  Arash Farhoodfar ,  Stewart Crozier ,  Frank R. Kschischang ,  Andrew Hunt

IPC: H04L25/34 ,  H03M13/29 ,  H04L1/00 ,  H04L25/49 ,  H04L27/04 ,  H03M13/15

Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.