-
公开(公告)号：US10601449B2
公开(公告)日：2020-03-24
申请号：US16575236
申请日：2019-09-18
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
-
公开(公告)号：US10320425B2
公开(公告)日：2019-06-11
申请号：US15194432
申请日：2016-06-27
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Frank R. Kschischang , Andrew Hunt , Benjamin P. Smith , John Lodge
Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1T Bi] and each column in [ B i B i + 1 T ] , for example, is a valid codeword.
-
Patent Agency Ranking
公开(公告)号：US10033410B2
公开(公告)日：2018-07-24
申请号：US15206011
申请日：2016-07-08
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
-
公开(公告)号：US10567005B2
公开(公告)日：2020-02-18
申请号：US16134311
申请日：2018-09-18
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Frank R. Kschischang , Benjamin P. Smith , Andrew Hunt
Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
-
公开(公告)号：US10461781B2
公开(公告)日：2019-10-29
申请号：US16011483
申请日：2018-06-18
Applicant: INPHI CORPORATION
Inventor： Benjamin Smith , Arash Farhoodfar , Stewart Crozier , Frank R. Kschischang , Andrew Hunt
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
-
公开(公告)号：US10110252B2
公开(公告)日：2018-10-23
申请号：US15378904
申请日：2016-12-14
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Frank R. Kschischang , Benjamin P. Smith , Andrew Hunt
Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
-
公开(公告)号：US10944430B2
公开(公告)日：2021-03-09
申请号：US16733815
申请日：2020-01-03
Applicant: INPHI CORPORATION
Inventor： Arash Farhoodfar , Frank R. Kschischang , Benjamin P. Smith , Andrew Hunt
Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
-
-
-
-
-
-
Search Results
7
records
(took 0.016 seconds)
