公开(公告)号：US11366636B2

公开(公告)日：2022-06-21

申请号：US16919022

申请日：2020-07-01

Applicant: INTEL CORPORATION

Inventor： Aditya Varma ,  Michael Espig

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/483 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

公开(公告)号：US20220342641A1

公开(公告)日：2022-10-27

申请号：US17839905

申请日：2022-06-14

Applicant: INTEL CORPORATION

Inventor： Aditya Varma ,  Michael Espig

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/483

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

公开(公告)号：US10713012B2

公开(公告)日：2020-07-14

申请号：US16160853

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Aditya Varma ,  Michael Espig

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/483 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying a multiply-accumulate or multiply-add operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range; control circuitry, responsive to a precision of the first and second operands being below a threshold, to cause the first operand and second operand to be processed by the second multiplication circuitry to generate the result; and adder circuitry to add the result to an accumulated value to generate a new accumulated value.

公开(公告)号：US11836464B2

公开(公告)日：2023-12-05

申请号：US17839905

申请日：2022-06-14

Applicant: INTEL CORPORATION

Inventor： Aditya Varma ,  Michael Espig

IPC: G06F7/544 ,  G06F7/533 ,  G06F9/30 ,  G06F7/483 ,  G06N3/063 ,  G06N3/045

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/533 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30112 ,  G06F2207/3812 ,  G06N3/045 ,  G06N3/063

Abstract: An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

公开(公告)号：US20220365751A1

公开(公告)日：2022-11-17

申请号：US17358722

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Aditya Varma ,  Mahesh Kumashikar ,  Michael Espig

IPC: G06F7/53 ,  G06F7/502 ,  G06F15/80

Abstract: An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.