公开(公告)号：US20180027177A1

公开(公告)日：2018-01-25

申请号：US15550699

申请日：2015-03-23

Applicant: INTEL CORPORATION

Inventor： YUNBIAO LIN ,  JIANHUI DAI ,  NING LUO ,  CHUNBO CHEN

IPC: H04N5/232 ,  G06F9/50 ,  G06F9/48 ,  H04N5/76 ,  H04N5/225

CPC classification number: H04N5/23229 ,  G06F9/4881 ,  G06F9/505 ,  H04N5/2257 ,  H04N5/232 ,  H04N5/23216 ,  H04N5/23241 ,  H04N5/23245 ,  H04N5/23293 ,  H04N5/3765 ,  H04N5/76 ,  H04N5/772

Abstract: Techniques are disclosed to control a camera device such that memory contention and power consumption is reduced during video processing routines, generally referred to herein as media tasks. In particular, a workload scheduler is implemented in a camera HAL and is configured to dispatch captured image frames in an alternating manner between competing media tasks such that the processing of those image frames is performed sequentially, and thus, eliminates or otherwise mitigates memory contention. To this end, techniques variously disclosed herein can be used to enable low-cost, low-memory configured devices to perform concurrent media tasks on captured high-definition video at high framerates, without an undesirable decrease in performance and an increase in power consumption.