公开(公告)号：US20240289213A1

公开(公告)日：2024-08-29

申请号：US18572226

申请日：2022-12-17

Applicant: INTEL CORPORATION

Inventor： Qiuxu ZHUO ,  Karthik ANANTHANARAYANAN ,  Hsing-Min CHEN ,  John HOLM ,  Anthony LUCK

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.