公开(公告)号：US20240289213A1

公开(公告)日：2024-08-29

申请号：US18572226

申请日：2022-12-17

Applicant: INTEL CORPORATION

Inventor： Qiuxu ZHUO ,  Karthik ANANTHANARAYANAN ,  Hsing-Min CHEN ,  John HOLM ,  Anthony LUCK

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and a second circuit to generate a generated ECC for the compacted data block. The apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC. Other embodiments are described and claimed.

公开(公告)号：US20220350500A1

公开(公告)日：2022-11-03

申请号：US17855688

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Wei P. CHEN ,  Theodros YIGZAW ,  Sarathy JAYAKUMAR ,  Anthony LUCK ,  Deep K. BUCH ,  Rajat AGARWAL ,  Kuljit S. BAINS ,  John G. HOLM ,  Brent CHARTRAND ,  Keith KLAYMAN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.