公开(公告)号：US12130702B2

公开(公告)日：2024-10-29

申请号：US17880220

申请日：2022-08-03

申请人： Micron Technology, Inc.

发明人： Melissa I. Uribe

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1048 ,  G06F11/1076

摘要： Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

公开(公告)号：US20240354191A1

公开(公告)日：2024-10-24

申请号：US18649031

申请日：2024-04-29

申请人： Rambus Inc.

发明人： Michael Raymond MILLER ,  Stephen Magee ,  John Eric Linstadt

IPC分类号： G06F11/10 ,  G06F3/06

CPC分类号： G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

摘要： Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20240338275A1

公开(公告)日：2024-10-10

申请号：US18232105

申请日：2023-08-09

申请人： Western Digital Technologies, Inc.

发明人： Ariel Navon ,  Shay Benisty ,  Alexander Bazarsky ,  Daniel Joseph Linnen ,  William Bernard Boyle

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048

摘要： Data storage devices configured to exploit generative-adversarial-networks (GANs) are described herein, including super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated. System and method examples are provided.

公开(公告)号：US20240282389A1

公开(公告)日：2024-08-22

申请号：US18654302

申请日：2024-05-03

申请人： Kioxia Corporation

发明人： Hiroyuki NAGASHIMA

IPC分类号： G11C16/26 ,  G06F11/10 ,  G06F11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  G06F11/3466 ,  G06F2201/88 ,  G11C16/0483

摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

公开(公告)号：US12067396B2

公开(公告)日：2024-08-20

申请号：US17557162

申请日：2021-12-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Timothy D. Anderson

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F9/3858 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

摘要： Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.

公开(公告)号：US12067239B2

公开(公告)日：2024-08-20

申请号：US17955907

申请日：2022-09-29

申请人： Micron Technology, Inc.

发明人： Marco Sforzin ,  Paolo Amato ,  Daniele Balluchi

IPC分类号： G06F11/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10

CPC分类号： G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/076 ,  G06F11/1004 ,  G06F11/1048

摘要： Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

公开(公告)号：US20240272980A1

公开(公告)日：2024-08-15

申请号：US18444320

申请日：2024-02-16

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Brent Steven Haukness

IPC分类号： G06F11/10 ,  G06F12/02 ,  G11C29/52

CPC分类号： G06F11/1008 ,  G06F11/1048 ,  G06F12/0246 ,  G11C29/52

摘要： A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US20240272836A1

公开(公告)日：2024-08-15

申请号：US18639808

申请日：2024-04-18

申请人： SK hynix Inc.

发明人： Won Ha Choi

IPC分类号： G06F3/06 ,  G06F11/10

CPC分类号： G06F3/068 ,  G06F3/061 ,  G06F3/0659 ,  G06F11/1048

摘要： A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.

公开(公告)号：US12050914B2

公开(公告)日：2024-07-30

申请号：US17472877

申请日：2021-09-13

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC分类号： G06F11/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F16/215 ,  G06F12/02 ,  G06F12/0862

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F9/3822 ,  G06F11/10 ,  G06F12/0207 ,  G06F12/0862 ,  G06F2212/1056 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/657 ,  G06F2212/681

摘要： A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US12045617B2

公开(公告)日：2024-07-23

申请号：US17670611

申请日：2022-02-14

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： William Franklin Leven ,  Asheesh Bhardwaj ,  Son Hung Tran ,  Timothy David Anderson

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897 ,  G06F17/16

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F17/16 ,  G06F2212/452 ,  G06F2212/60

摘要： Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.