公开(公告)号：US10164912B2

公开(公告)日：2018-12-25

申请号：US15218681

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  David L. Chalupsky ,  Kevan A. Lillie ,  Richard I. Mellitz ,  Kent C. Lusted

IPC: H04L12/935

Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

公开(公告)号：US20180331907A1

公开(公告)日：2018-11-15

申请号：US16044122

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04L12/24

CPC classification number: H04L41/0886 ,  H04L49/3054 ,  H04L69/24

Abstract: Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.

公开(公告)号：US09602401B2

公开(公告)日：2017-03-21

申请号：US14580737

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  Kent C. Lusted

IPC: H03M13/03 ,  H04L12/721 ,  H04L1/00 ,  H03M13/25

CPC classification number: H04L45/66 ,  H03M13/25 ,  H03M13/251 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0083

Abstract: Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66 b/64 b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.

公开(公告)号：US09264270B2

公开(公告)日：2016-02-16

申请号：US13928648

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H03C1/52 ,  H04L27/04 ,  H04L25/49 ,  H04L25/03 ,  H04B17/10

CPC classification number: H04L25/4917 ,  H04B17/104 ,  H04L25/03343

Abstract: Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmit a PAM4 symbol test pattern, which is captured as a signal waveform. The test pattern includes at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured for at least one rising signal sequence and falling signal sequence to derive 20% and 80% VMA levels. A rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and a fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

Abstract translation: 用于测量四电平脉冲调制幅度（PAM4）发射机的信号转换时间的方法，装置和系统。 在测试过程中，PAM4发射机被配置为重复地发送作为信号波形捕获的PAM4符号测试模式。 测试图案包括至少一个上升信号序列，其具有至少三个-1个PAM4符号的PAM4符号图案，其后跟至少三个+1PAM4符号，以及至少一个具有至少三个+1的PAM4符号图案的下降信号序列 PAM4符号后跟至少三个-1 PAM4符号。 对于至少一个上升信号序列和下降信号序列测量-1和+1个PAM4信号电平中的每一个的电压调制幅度（VMA）电平以得到20％和80％的VMA电平。 然后通过测量上升信号跨越20％和80％VMA电平之间的时间间隔来确定升高转变时间，并且通过测量下降信号跨越80％和20之间的时间间隔来确定下降转变时间 ％VMA级别。

公开(公告)号：US20150003505A1

公开(公告)日：2015-01-01

申请号：US13928648

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04B17/00 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04B17/104 ,  H04L25/03343

Abstract: Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmit a PAM4 symbol test pattern, which is captured as a signal waveform. The test pattern includes at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured for at least one rising signal sequence and falling signal sequence to derive 20% and 80% VMA levels. A rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and a fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

Abstract translation: 用于测量四电平脉冲调制幅度（PAM4）发射机的信号转换时间的方法，装置和系统。 在测试过程中，PAM4发射机被配置为重复地发送作为信号波形捕获的PAM4符号测试模式。 测试图案包括至少一个上升信号序列，其具有至少三个-1个PAM4符号的PAM4符号图案，其后跟至少三个+1PAM4符号，以及至少一个具有至少三个+1的PAM4符号图案的下降信号序列 PAM4符号后跟至少三个-1 PAM4符号。 对于至少一个上升信号序列和下降信号序列测量-1和+1个PAM4信号电平中的每一个的电压调制幅度（VMA）电平以得到20％和80％的VMA电平。 然后通过测量上升信号跨越20％和80％VMA电平之间的时间间隔来确定升高转变时间，并且通过测量下降信号跨越80％和20之间的时间间隔来确定下降转变时间 ％VMA级别。

公开(公告)号：US12160492B2

公开(公告)日：2024-12-03

申请号：US18374475

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kent C. Lusted

IPC: H04L69/24 ,  H04L49/00 ,  H04L49/351 ,  H04L69/324

Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.

公开(公告)号：US11277308B2

公开(公告)日：2022-03-15

申请号：US16847336

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04L41/08 ,  H04L69/24 ,  H04L49/00

Abstract: Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotiation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.

公开(公告)号：US20200244535A1

公开(公告)日：2020-07-30

申请号：US16847336

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04L12/24

Abstract: Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotiation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.

公开(公告)号：US20180139015A1

公开(公告)日：2018-05-17

申请号：US15820183

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  Kent C. Lusted

IPC: H04L1/24 ,  H04L1/20

CPC classification number: H04L1/248 ,  H04L1/203 ,  H04L1/244

Abstract: One embodiment provides an apparatus. The example apparatus includes a root mean square (RMS) distortion determination module configured to determine an RMS distortion error and a signal to noise and distortion ratio (SNDR), the RMS distortion error determined based, at least in part, on a portion of a transmitted pulse centered at or near a transmitted pulse maximum amplitude and the SNDR determined based, at least in part, on the RMS distortion error.

公开(公告)号：US09231740B2

公开(公告)日：2016-01-05

申请号：US14142308

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Adee Ranjan ,  Kent C. Lusted

IPC: H04L1/20 ,  H04L1/24

CPC classification number: H04L1/248 ,  H04L1/203 ,  H04L1/244

Abstract: One embodiment provides an apparatus. The example apparatus includes a root mean square (RMS) distortion determination module configured to determine an RMS distortion error and a signal to noise and distortion ratio (SNDR), the RMS distortion error determined based, at least in part, on a portion of a transmitted pulse centered at or near a transmitted pulse maximum amplitude and the SNDR determined based, at least in part, on the RMS distortion error.

Abstract translation: 一个实施例提供了一种装置。 所述示例性装置包括均方根（RMS）失真确定模块，其被配置为确定RMS失真误差和信噪比和失真比（SNDR），所述RMS失真误差至少部分地基于 至少部分地基于RMS失真误差确定基于发射脉冲最大幅度或接近传输脉冲最大振幅的发射脉冲。