公开(公告)号：US20160179549A1

公开(公告)日：2016-06-23

申请号：US14580498

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： POLYCHRONIS XEKALAKIS ,  JAMISON D. COLLINS ,  SUMIT AHUJA

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3818 ,  G06F9/3005 ,  G06F9/3842 ,  G06F9/3846

Abstract: A processor includes a front end including a decoder to decode a branch instruction to perform a branch operation. The processor includes a loop stream unit with logic to identify from the branch instruction that the branch operation is a loop operation, determine whether the loop operation will include a fixed or effectively-infinite number of iterations, load decoded instructions of a loop iteration of the loop operation, and cyclically issue the decoded instructions of the loop iteration in a manner based upon whether the loop operation will include a fixed or effectively-infinite number of iterations. The processor also includes an execution unit to execute the branch instruction and a retirement unit including to retire the branch instruction.

Abstract translation: 处理器包括前端，其包括用于解码分支指令以执行分支操作的解码器。 处理器包括具有逻辑的循环流单元，用于从分支指令中识别分支操作是循环操作，确定循环操作是否包括固定或有效无限次数的迭代，将解码的指令循环迭代 循环操作，并且基于循环操作是否将包括固定或无限次迭代次数的方式循环地发布循环迭代的解码指令。 处理器还包括执行分支指令的执行单元和退出分支指令的退休单元。