公开(公告)号：US20150277916A1

公开(公告)日：2015-10-01

申请号：US14228690

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： DENIS M. KHARTIKOV ,  NAVEEN NEELAKANTAM ,  JOHN H. KELM ,  POLYCHRONIS XEKALAKIS

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

Abstract translation: 用于优化的动态无序超长指令字（VLIW）管道的硬件/软件协同设计。 例如，一种装置的一个实施例包括：指令提取单元，用于从存储器以其程序顺序获取超长指令字（VLIW），每个VLIW包括分组到多个指令集计算（RISC）指令音节中的多个简化指令集计算（RISC）指令音节 VLIWs以一个顺序消除数据流依赖性和错误输出依赖关系之间的音节; 解码单元，以编程顺序对VLIW进行解码，并并行输出每个经解码的VLIW的音节; 以及优先与其他音节并行地执行音节的无序执行引擎，其中至少一些音节将以与从解码单元接收的顺序不同的顺序执行，出口 具有一个或多个处理阶段的执行引擎，当执行操作时，该处理阶段不检查数据流依赖性和音节之间的错误输出依赖性。

公开(公告)号：US20180067731A1

公开(公告)日：2018-03-08

申请号：US15813021

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： POLYCHRONIS XEKALAKIS ,  JASON M. AGRON

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/455 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F8/41 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3806 ,  G06F9/4484 ,  G06F9/455 ,  G06F9/4552

Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

公开(公告)号：US20160283234A1

公开(公告)日：2016-09-29

申请号：US14672158

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： POLYCHRONIS XEKALAKIS ,  Jamison D. Collins ,  Jason M. Agron

IPC: G06F9/30

CPC classification number: G06F9/455 ,  G06F9/45516

Abstract: Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.

Abstract translation: 与防止修改指令的执行有关的方法和装置。 在一个实施例中，一种装置包括用于将指令转换为转换的指令的硬件二进制转换器和一致性硬件管理器，以防止硬件处理器在检测到对虚拟对物理地址映射的修改时执行转换的指令 翻译后的指示。

公开(公告)号：US20170300334A1

公开(公告)日：2017-10-19

申请号：US15477374

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： DENIS M. KHARTIKOV ,  NAVEEN NEELAKANTAM ,  JOHN H. KELM ,  POLYCHRONIS XEKALAKIS

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

公开(公告)号：US20160179549A1

公开(公告)日：2016-06-23

申请号：US14580498

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： POLYCHRONIS XEKALAKIS ,  JAMISON D. COLLINS ,  SUMIT AHUJA

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3818 ,  G06F9/3005 ,  G06F9/3842 ,  G06F9/3846

Abstract: A processor includes a front end including a decoder to decode a branch instruction to perform a branch operation. The processor includes a loop stream unit with logic to identify from the branch instruction that the branch operation is a loop operation, determine whether the loop operation will include a fixed or effectively-infinite number of iterations, load decoded instructions of a loop iteration of the loop operation, and cyclically issue the decoded instructions of the loop iteration in a manner based upon whether the loop operation will include a fixed or effectively-infinite number of iterations. The processor also includes an execution unit to execute the branch instruction and a retirement unit including to retire the branch instruction.

Abstract translation: 处理器包括前端，其包括用于解码分支指令以执行分支操作的解码器。 处理器包括具有逻辑的循环流单元，用于从分支指令中识别分支操作是循环操作，确定循环操作是否包括固定或有效无限次数的迭代，将解码的指令循环迭代 循环操作，并且基于循环操作是否将包括固定或无限次迭代次数的方式循环地发布循环迭代的解码指令。 处理器还包括执行分支指令的执行单元和退出分支指令的退休单元。