公开(公告)号：US11113159B2

公开(公告)日：2021-09-07

申请号：US16616905

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Zhiyuan Zhang ,  Xiangbin Wu ,  Xinxin Zhang ,  Qianying Zhu ,  Haitao Ji ,  Yingzhe Shen

IPC: G06F11/14 ,  G06F12/16 ,  G06F17/40 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.

公开(公告)号：US10581997B2

公开(公告)日：2020-03-03

申请号：US15549146

申请日：2015-03-05

Applicant: INTEL CORPORATION

Inventor： Shunyu Zhu ,  Xiangbin Wu ,  Zhiyuan Zhang ,  Xinxin Zhang ,  Qianying Zhu

IPC: G06F13/00 ,  H04L29/08 ,  G06F16/958 ,  G06F16/21 ,  G06F16/22

Abstract: Examples may include techniques for storing or accessing a key-value (KV) item stored in a memory that is part of a memcached system. A KV server coupled with a network input/output device may be capable of allocating one or more item slots from the memory and indicating to logic or features of the network input/output device whether the KV item is stored in a single allocated item slot of the memory, accessible via multiple allocated item slots of the memory or whether the KV item is being updated.

公开(公告)号：US10306673B2

公开(公告)日：2019-05-28

申请号：US15300042

申请日：2014-05-12

Applicant: Intel Corporation

Inventor： Zhiyuan Zhang ,  Qianying Zhu ,  Xinxin Zhang ,  Shunyu Zhu ,  Xiangbin Wu ,  Xuebin Yang ,  Senjie Zhang ,  Guangjie Li ,  Xu Zhang

IPC: H04W74/00 ,  H04L27/26 ,  H04L5/00 ,  H04W56/00 ,  H04W74/08 ,  H03M7/30 ,  H04W88/08

Abstract: A front-end unit that operates within a C-RAN architecture to perform the functions of cellular signal processing and resource selection between an RRU and the BBU pool network is described. The front-end unit supports flexible load migration and CoMP (coordinated multipoint) in the CRAN BBU while also reducing data transmission within the BBU pool network or between the BBU pool network and the RRU.

公开(公告)号：US11474736B2

公开(公告)日：2022-10-18

申请号：US16465107

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zhiyuan Zhang ,  Xiangbin Wu ,  Qianying Zhu ,  Xinxin Zhang ,  Yingzhe Shen ,  Haitao Ji

IPC: G06F3/06

Abstract: Embodiments of the present disclosure provide devices, techniques, and configurations for network interface controllers (NICs) that log write packets received from a network in non-volatile random access memory (NVRAM). In one embodiment, a NIC includes a network interface to couple a host of the NIC to a network, a NVRAM, and a controller coupled with the network interface and the NVRAM, where the controller is to log write packets received at the network interface from the network in the NVRAM. Other embodiments may be described and/or claimed.

公开(公告)号：US20170251493A1

公开(公告)日：2017-08-31

申请号：US15300042

申请日：2014-05-12

Applicant: INTEL CORPORATION

Inventor： Zhiyuan Zhang

IPC: H04W74/00 ,  H04W56/00 ,  H04L5/00 ,  H04L27/26 ,  H04W74/08

CPC classification number: H04W74/002 ,  H03M7/30 ,  H03M7/3068 ,  H04L5/0007 ,  H04L5/0048 ,  H04L27/2607 ,  H04L27/2626 ,  H04L27/2628 ,  H04L27/2647 ,  H04W56/001 ,  H04W74/0833 ,  H04W88/085

Abstract: A front-end unit that operates within a C-RAN architecture to perform the functions of cellular signal processing and resource selection between an RRU and the BBU pool network is described. The front-end unit supports flexible load migration and CoMP (coordinated multipoint) in the CRAN BBU while also reducing data transmission within the BBU pool network or between the BBU pool network and the RRU.