公开(公告)号：US20150170923A1

公开(公告)日：2015-06-18

申请号：US14133546

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Federico Nardi ,  Randall J. Higuchi ,  Robert A. Huertas ,  Yun Wang

IPC: H01L21/306

CPC classification number: H01L21/32134 ,  H01L21/28123 ,  H01L21/32139 ,  H01L28/20 ,  H01L29/66545

Abstract: Selective wet etching is used to produce feature sizes of reduced width in semiconductor devices. An initial patterning step (e.g., photolithography) forms a pillar of an initial width from at least a selected first layer and an overlayer. A wet etchant that is selective to the selected layer undercuts the sidewalls of the selected layer to a smaller width while leaving at least part of the overlayer in place to protect the top surface of the selected layer. The selected layer becomes a narrow “stem” within the pillar, and may have dimensions below the resolution limit of the technique used for the initial patterning. For some devices, voids may be intentionally left in a fill layer around the stem for electrical or thermal insulation.

Abstract translation: 选择性湿蚀刻用于制造半导体器件中宽度减小的特征尺寸。 初始构图步骤（例如，光刻）从至少所选择的第一层和覆盖层形成初始宽度的柱。 对所选择的层选择性的湿蚀刻剂将所选层的侧壁切割成更小的宽度，同时使覆盖层的至少一部分保留在适当位置以保护所选择的层的顶表面。 所选择的层在柱内成为窄的“茎”，并且可以具有低于用于初始图案化的技术的分辨率极限的尺寸。 对于一些设备，可能有意将空隙留在阀杆周围的填充层中进行电气或绝热。

公开(公告)号：US09018037B1

公开(公告)日：2015-04-28

申请号：US14098263

申请日：2013-12-05

Applicant: Intermolecular, Inc.

Inventor： Federico Nardi ,  Randall J. Higuchi ,  Robert A. Huertas ,  Yun Wang

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1666

Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.

Abstract translation: 形成具有垂直接口的电阻式开关层可以产生沿着两个电极之间的界面限制的缺陷。 限制缺陷可以形成用于灯丝形成和溶解的预定区域，导致低功率电阻切换和低编程电压或电流变化。 此外，由于限制缺陷的存在，可以省略电阻式存储器件的灯丝形成工艺。

公开(公告)号：US20140154859A1

公开(公告)日：2014-06-05

申请号：US13705516

申请日：2012-12-05

Applicant: INTERMOLECULAR INC.

Inventor： Vidyut Gopal ,  Tony P. Chiang ,  Imran Hashim ,  Randall J. Higuchi ,  Robert A. Huertas ,  Hieu Pham ,  Yun Wang

IPC: H01L49/02

CPC classification number: H01L22/34 ,  H01L45/08 ,  H01L45/145

Abstract: Provided are methods for processing different materials on the same substrate for high throughput screening of multiple ReRAM materials. A substrate may be divided into multiple site isolated regions, each region including one or more base structures operable as bottom electrodes of ReRAM cells. Different test samples may be formed over these base structures in a combinatorial manner. Specifically, each site isolated region may receive a test sample that has a different characteristic than at least one other sample provided in another region. The test samples may have different compositions and/or thicknesses or be deposited using different techniques. These different samples are then etched in the same operation to form portions of the samples. Each portion is substantially larger than the corresponding base structure and fully covers this base structure to protect the interface between the base structure and the portion during etching.

Abstract translation: 提供了在同一基板上处理不同材料的方法，用于多个ReRAM材料的高通量筛选。 衬底可以被分成多个位置隔离区域，每个区域包括可操作为ReRAM单元的底部电极的一个或多个基底结构。 可以以组合的方式在这些基础结构上形成不同的测试样品。 具体地说，每个位置隔离区域可以接收具有与另一区域中提供的至少一个其他样品不同的特性的测试样品。 测试样品可以具有不同的组成和/或厚度或使用不同的技术沉积。 然后在相同的操作中蚀刻这些不同的样品以形成样品的一部分。 每个部分基本上大于对应的基部结构，并且完全覆盖该基部结构以在蚀刻期间保护基部结构和该部分之间的界面。