公开(公告)号：US12129418B2

公开(公告)日：2024-10-29

申请号：US17743080

申请日：2022-05-12

Applicant: ENTEGRIS, INC.

Inventor： Hsing-Chen Wu ,  Min-Chieh Yang ,  Ming-Chi Liao ,  Wen Hua Tai ,  Wei-Ling Lan

IPC: C09K13/06 ,  C09K13/00 ,  C09K13/04 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC classification number: C09K13/06 ,  C09K13/00 ,  C09K13/04 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31105 ,  H01L21/32134

Abstract: The present invention relates to compositions and methods for selectively etching silicon nitride in the presence of silicon oxide, polysilicon and/or metal silicides at a high etch rate and with high selectivity. Additives are described that can be used at various dissolved silica loading windows to provide and maintain the high selective etch rate and selectivity.

公开(公告)号：US12110436B2

公开(公告)日：2024-10-08

申请号：US17756223

申请日：2020-09-30

Applicant: Versum Materials US, LLC

Inventor： Chung-Yi Chang ,  Wen Dar Liu ,  Yi-Chia Lee

IPC: C09K13/08 ,  C09K13/06 ,  H01L21/3213

CPC classification number: C09K13/08 ,  C09K13/06 ,  H01L21/32134

Abstract: The disclosed and claimed subject matter relates to wet etchants exhibiting high copper and cobalt etching rates where the etching rate ratio between the two metals can be varied. The wet etchants have a composition comprising a formulation consisting of: at least one alkanolamine having at least two carbon atoms, at least one amino substituent and at least one hydroxyl substituent with the amino and hydroxyl substituents attached to two different carbon atoms; at least one pH adjuster for adjusting the pH of the formulation to between approximately 9 and approximately 12; at least one chelating agent; and water.

公开(公告)号：US20240287384A1

公开(公告)日：2024-08-29

申请号：US18583264

申请日：2024-02-21

Applicant: Fujifilm Electronic Materials U.S.A., Inc.

Inventor： Joshua Guske ,  Atsushi Mizutani

IPC: C09K13/02 ,  C09K13/00 ,  C09K15/30 ,  H01L21/02 ,  H01L21/3213

CPC classification number: C09K13/02 ,  C09K13/00 ,  C09K15/30 ,  H01L21/02071 ,  H01L21/32134

Abstract: The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing tantalum nitride (TaN) from a semiconductor substrate.

公开(公告)号：US12068385B2

公开(公告)日：2024-08-20

申请号：US17446218

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： U-Ting Chiu ,  Chun-Cheng Chou ,  Chi-Shin Wang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/76877 ,  H01L23/528 ,  H01L29/41725

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

公开(公告)号：US20240234214A1

公开(公告)日：2024-07-11

申请号：US18615403

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu ,  Kuo-Cheng Chiang

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42372

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

公开(公告)号：US20240217868A1

公开(公告)日：2024-07-04

申请号：US18090505

申请日：2022-12-29

Applicant: Industrial Technology Research Institute

Inventor： Hao-Wen Cheng ,  Ming-Huei Yen ,  Wen-Jin Li ,  Yu-Ting Guan ,  Ding-Shiang Wang

IPC: C03C15/00 ,  H01L21/3213

CPC classification number: C03C15/00 ,  H01L21/32134

Abstract: A method of performing a selective etch on an array substrate including the following is provided, and the array substrate includes a substrate and a component layer disposed on the substrate. Deionized water, hydrogen peroxide, and an acid are mixed to prepare a first solution, and the acid includes sulfuric acid, hydrochloric acid, oxalic acid or a combination thereof. An alkoxy silane compound is added to the first solution to prepare a second solution. The array substrate is placed into the second solution to remove the component layer, and an aging second solution is formed. The substrate is taken out from the aging second solution.

公开(公告)号：US12027626B2

公开(公告)日：2024-07-02

申请号：US18066188

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/78 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7856 ,  H01L21/3065 ,  H01L21/32134 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

公开(公告)号：US12020947B2

公开(公告)日：2024-06-25

申请号：US17379431

申请日：2021-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-An Han ,  Ding-I Liu ,  Yuh-Ta Fan ,  Kai-Shiung Hsu

IPC: H01L29/49 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/32134 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/3215 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

公开(公告)号：US12015068B2

公开(公告)日：2024-06-18

申请号：US17713168

申请日：2022-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Bo-Wen Hsieh ,  Yi-Chun Lo ,  Wen-Jia Hsieh

IPC: H01L29/423 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/0276 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/513 ,  H01L29/517

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

公开(公告)号：US20240153826A1

公开(公告)日：2024-05-09

申请号：US18410589

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Chi Huang ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823821

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.