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公开(公告)号：US20240081158A1
公开(公告)日：2024-03-07
申请号：US17950049
申请日：2022-09-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei Cheng , ZHEN CHEN , Shen-De Wang
CPC classification number: H01L45/1675 , H01L27/2463 , H01L45/1233
Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.
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公开(公告)号：US20230413698A1
公开(公告)日：2023-12-21
申请号：US17876560
申请日：2022-07-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wen-Jen Wang , Chun-Hung Cheng , Chuan-Fu Wang
CPC classification number: H01L45/146 , H01L45/1253 , H01L45/1675 , H01L45/1683 , H01L45/1608 , H01L27/2463
Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
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3.发明公开公开(公告)号：US20230371282A1
公开(公告)日：2023-11-16
申请号：US17742154
申请日：2022-05-11
Applicant: Micron Technology, Inc.
Inventor： David A. Kewley , Kevin Baker , Trupti D. Gawai
CPC classification number: H01L27/2463 , G11C13/0023 , G11C2213/77
Abstract: Integrated circuitry comprises a horizontally-elongated insulative wall directly above a conductive node. The wall comprises insulative material. A conductive via extends through the wall to the conductive node. A conductive line is directly above the wall and directly above the conductive via. The conductive via directly electrically couples together the conductive line with the conductive node. Insulator material is longitudinally-along laterally-opposing sides of the wall. An interface of the insulative material of the wall and the insulator material are on each of the laterally-opposing sides of the wall. Other embodiments, including method, are disclosed.
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公开(公告)号：US20230200265A1
公开(公告)日：2023-06-22
申请号：US17552429
申请日：2021-12-16
Applicant: International Business Machines Corporation
Inventor： Kevin W. Brew , Injo Ok , Sanjay C. Mehta , Matthew T. Shoudy , Nicole Saulnier , Iqbal Rashid Saraf
CPC classification number: H01L45/06 , H01L45/145 , H01L45/1675 , H01L45/1691 , H01L45/1253 , H01L45/1608 , H01L45/1683 , H01L27/2463
Abstract: A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.
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公开(公告)号：US11683942B2
公开(公告)日：2023-06-20
申请号：US16616233
申请日：2018-05-01
Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor： Jun Sumino , Masayuki Tazaki , Hideyuki Fukata
IPC: H01L23/522 , H01L27/24 , H01L23/528 , H01L45/00
CPC classification number: H01L27/2463 , H01L23/528 , H01L23/5226 , H01L27/2427 , H01L45/08 , H01L45/1233 , H01L45/144 , H01L45/16
Abstract: A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.
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Patent Agency Ranking
公开(公告)号：US20230187314A1
公开(公告)日：2023-06-15
申请号：US17551457
申请日：2021-12-15
Applicant: International Business Machines Corporation
Inventor： Biswanath Senapati , Seiji Munetoh , Nicholas Anthony Lanzillo , Lawrence A. Clevenger , Geoffrey Burr , Kohji Hosokawa
IPC: H01L23/48 , H01L27/24 , H01L23/532 , H01L21/768 , G11C13/00
CPC classification number: H01L23/481 , G11C13/0004 , G11C13/0038 , H01L21/76898 , H01L23/53209 , H01L23/53242 , H01L23/53257 , H01L27/2463
Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.
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公开(公告)号：US20230146034A1
公开(公告)日：2023-05-11
申请号：US17454570
申请日：2021-11-11
Applicant: International Business Machines Corporation
Inventor： Michael Rizzolo , Devika Sarkar Grant , SON NGUYEN
CPC classification number: H01L27/2463 , H01L27/222 , H01L43/02 , H01L43/12 , H01L45/1253 , H01L45/16
Abstract: An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.
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公开(公告)号：US11647680B2
公开(公告)日：2023-05-09
申请号：US16898527
申请日：2020-06-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Takashi Ando , Hiroyuki Miyazoe , Eduard Albert Cartier , Babar Khan , Youngseok Kim , Dexin Kong , Soon-Cheon Seo , Joel P. De Souza
CPC classification number: H01L45/1641 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1608
Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.
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公开(公告)号：US20190214560A1
公开(公告)日：2019-07-11
申请号：US16352443
申请日：2019-03-13
Applicant: International Business Machines Corporation
Inventor： Matthew J. BrightSky
CPC classification number: H01L45/1683 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1666
Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
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公开(公告)号：US20190214557A1
公开(公告)日：2019-07-11
申请号：US16246143
申请日：2019-01-11
Applicant: Xergy Inc.
Inventor： Bamdad Bahar
CPC classification number: H01L45/1246 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/146 , H01L45/1641
Abstract: An electrochemical neuromorphic organic device (ENODe) memristor has improved performance and lower power requirements through the use of highly conductive polymers, including ionomer, such as sulfonated tetrafluoroethylene based fluoropolymer-copolymer. These ionomers may be more conductive and may have a low equivalent weight. The ionomer may be reinforced with a support material, such as a thin porous polymer. The thickness of the layer may be reduced to no more than about 50 microns and in some cases no more than 5 microns. Other ionomer polymers include highly functionalized styrene-butadiene copolymers and biphynl based ionomers.
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