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1.发明授权Via structure, memory array structure, three-dimensional resistance memory and method of forming the same 有权通孔结构，存储阵列结构，三维电阻记忆及其形成方法公开(公告)号：US09257641B2
公开(公告)日：2016-02-09
申请号：US14488300
申请日：2014-09-17
Applicant: Industrial Technology Research Institute
Inventor： Frederick T. Chen , Tai-Yuan Wu , Yu-Sheng Chen , Wei-Su Chen , Pei-Yi Gu , Yu-De Lin
CPC classification number: H01L45/122 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1683 , H01L45/1691
Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
Abstract translation: 提供了包括层叠层的三维电阻存储器。 层叠层被封装在电介质层中，并且与封装介电层中的至少一个开口相邻。 至少一个L形可变电阻间隔件设置在邻近层叠层的开口的侧壁的至少一部分上。 电极层填充开口的剩余部分。
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2.发明申请VIA STRUCTURE, MEMORY ARRAY STRUCTURE, THREE-DIMENSIONAL RESISTANCE MEMORY AND METHOD OF FORMING THE SAME 有权通过结构，记忆阵列结构，三维电阻记忆及其形成方法公开(公告)号：US20150129827A1
公开(公告)日：2015-05-14
申请号：US14488300
申请日：2014-09-17
Applicant: Industrial Technology Research Institute
Inventor： Frederick T. Chen , Tai-Yuan Wu , Yu-Sheng Chen , Wei-Su Chen , Pei-Yi Gu , Yu-De Lin
CPC classification number: H01L45/122 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1683 , H01L45/1691
Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
Abstract translation: 提供了包括层叠层的三维电阻存储器。 层叠层被封装在电介质层中，并且与封装介电层中的至少一个开口相邻。 至少一个L形可变电阻间隔件设置在邻近层叠层的开口的侧壁的至少一部分上。 电极层填充开口的剩余部分。
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