公开(公告)号：US11676641B2

公开(公告)日：2023-06-13

申请号：US17461332

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh Lee ,  Yi-Ching Liu ,  Chia-En Huang ,  Chang Jen-Yuan ,  Yih Wang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H01L27/24 ,  H01L43/12 ,  H01L45/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  H01L23/481 ,  H01L27/108 ,  H01L27/222 ,  H01L27/2481 ,  H01L43/02 ,  H01L43/12 ,  H01L45/122 ,  H01L45/16

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

公开(公告)号：US20190148635A1

公开(公告)日：2019-05-16

申请号：US16225318

申请日：2018-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen

Inventor： Vara S. P. Jonnalagadda ,  Benedikt J. Kersting ,  Wabe W. Koelmans ,  Martin Salinga ,  Abu Sebastian

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/52 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148

Abstract: The invention is directed to a resistive memory device comprising a control unit for controlling a memory cell of the memory device. The memory cell includes a first terminal, a second terminal and a phase change segment comprising a phase-change material. The phase change segment is arranged between the first terminal and the second terminal. The phase change material is antimony. The phase change segment retains an amorphous region during a write operation. The control unit, during the write operation, applies an electrical programming pulse to the terminals to cause a portion of the phase change segment to transition from a crystalline phase to an amorphous phase comprising the amorphous region. A trailing edge duration of the electrical programming pulse is adjusted based on ambient temperature to prevent re-crystallization of the amorphous region. Shorter trailing edge durations are used at increasing ambient temperatures.

公开(公告)号：US20180375020A1

公开(公告)日：2018-12-27

申请号：US15837999

申请日：2017-12-11

Applicant: GULA CONSULTING LIMITED LIABILITY COMPANY

Inventor： Frederick T. Chen ,  Ming-Jinn Tsai

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/14 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1691

Abstract: A phase-change memory element is provided. The phase-change memory element may include an electrode; a phase-change material that contacts the electrode; a first conductor that contacts the phase-change material; and a second conductor that contacts the phase-change material. The second conductor may be electrically connected to the first conductor only through the phase-change material, and each of the first and second conductors may be electrically connected to the electrode only through the phase-change material.

公开(公告)号：US10038141B2

公开(公告)日：2018-07-31

申请号：US15463546

申请日：2017-03-20

Applicant: ARM Ltd.

Inventor： Carlos Alberto Paz de Araujo ,  Kimberly Gay Reid ,  Lucian Shifren

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L45/1616 ,  C23C16/45553 ,  C23C16/56 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1641

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.

公开(公告)号：US20180197732A1

公开(公告)日：2018-07-12

申请号：US15910583

申请日：2018-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-IK OH ,  DAEHYUN JANG ,  HA-NA KIM ,  KYOUNGSUB SHIN

IPC: H01L21/027 ,  H01L27/11575 ,  H01L21/308 ,  H01L27/11556 ,  H01L21/306 ,  H01L27/11582 ,  H01L27/24 ,  H01L25/00 ,  H01L27/11521 ,  H01L25/065 ,  H01L45/00

CPC classification number: H01L21/0274 ,  H01L21/30604 ,  H01L21/3085 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US20180190714A1

公开(公告)日：2018-07-05

申请号：US15849563

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L27/2436 ,  H01L21/82345 ,  H01L29/7869 ,  H01L45/065 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

公开(公告)号：US20180175108A1

公开(公告)日：2018-06-21

申请号：US15579302

申请日：2016-05-18

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Haruhiko TERADA

IPC: H01L27/24 ,  H01L27/22 ,  H01L23/528 ,  H01L45/00 ,  H01L27/11551 ,  G11C29/00

CPC classification number: H01L27/249 ,  G11C29/80 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/226 ,  H01L27/228 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1266

Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

公开(公告)号：US20180040816A1

公开(公告)日：2018-02-08

申请号：US15784689

申请日：2017-10-16

Applicant: Commissariat a L'energie Atomique et aux Energies Alternatives

Inventor： Gabriel MOLAS ,  Philippe BLAISE ,  Faiz DAHMANI ,  Elisa VIANELLO

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/122 ,  G11C13/0011 ,  G11C2213/56 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

公开(公告)号：US09887353B2

公开(公告)日：2018-02-06

申请号：US15293079

申请日：2016-10-13

Applicant: SK hynix Inc.

Inventor： Wan-Gee Kim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/124 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer.

公开(公告)号：US20180019390A1

公开(公告)日：2018-01-18

申请号：US15715413

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Chun You ,  Sheng-Hung Shih

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/122 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.