公开(公告)号：US09455045B1

公开(公告)日：2016-09-27

申请号：US14691472

申请日：2015-04-20

Applicant: Integrated Device Technology, Inc.

Inventor： Xiaohong Zheng ,  Hui Li

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/20 ,  G11C7/222 ,  G11C17/16

Abstract: The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.

Abstract translation: 本发明提供了一种方法和装置，其包括用于产生定时信号的定时装置电路，耦合到定时装置电路的RAM，OTP NVM和选择逻辑。 RAM可以在接收到刻录地址以从烧录地址开始读取RAM中的配置数据时操作，并且OTP NVM可操作地将从RAM读取的配置数据刻录到OTP NVM中。 OTP NVM被配置为读取OTP NVM中的配置数据，并且RAM被配置为从对应于读起始地址的RAM中的地址开始存储来自OTP NVM的配置数据，以定义RAM中的定时设备配置。