公开(公告)号：US20240347084A1

公开(公告)日：2024-10-17

申请号：US18755033

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

公开(公告)号：US12119082B2

公开(公告)日：2024-10-15

申请号：US17968374

申请日：2022-10-18

Applicant: SK hynix Inc.

Inventor： Sang Geun Bae ,  Seung Jin Park

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C2207/2254 ,  G11C2207/2281

Abstract: A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

公开(公告)号：US20240339140A1

公开(公告)日：2024-10-10

申请号：US18297094

申请日：2023-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SANJEEV KUMAR JAIN ,  ATUL KATOCH

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/12

Abstract: The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input/output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input/output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

公开(公告)号：US12106794B2

公开(公告)日：2024-10-01

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US12100474B2

公开(公告)日：2024-09-24

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong Xu ,  Satish Krishnamoorthy ,  Boris Dimitrov Andreev ,  Patrick Isakanian ,  Farrukh Aquil ,  Vikas Mahendiyan ,  Ravindra Arvind Khedkar

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US20240312502A1

公开(公告)日：2024-09-19

申请号：US18497747

申请日：2023-10-30

Applicant: SK hynix Inc.

Inventor： Ji Hyo KANG

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1057

Abstract: A clock distribution network includes at least two buffers that receive the same clock signal and generate different clock signals. In a first operation mode, the at least two buffers are all activated. In a second operation mode, one of the at least two buffers is activated. In the second operation mode, the other one of the at least two buffers is partially activated without being deactivated.

公开(公告)号：US20240312500A1

公开(公告)日：2024-09-19

申请号：US18462254

申请日：2023-09-06

Applicant: SK hynix Inc.

Inventor： Mino KIM ,  Sungwoo LEE

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/222 ,  G11C8/10

Abstract: A semiconductor apparatus includes a power gating control circuit and a power gating circuit. The power gating control circuit generates a power gating signal based on an idle signal, a clock synchronization signal, and a delayed idle signal. The power gating circuit applies at least a first operating voltage to an internal circuit based on the power gating signal.

公开(公告)号：US12094560B2

公开(公告)日：2024-09-17

申请号：US17812102

申请日：2022-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Huipeng Ba ,  Yuan He

IPC: G11C11/00 ,  G11C7/04 ,  G11C7/22

CPC classification number: G11C7/04 ,  G11C7/222

Abstract: Apparatuses, systems, and methods for accurate bias temperature instability (BTI) mitigation. During a first period a signal is provided to a path of a device, and during a second period a BTI toggle signal is provided to the path. During the first period a ratio of the time that the signal is active or inactive is measured. During the second period the BTI toggle signal is provided with a duty cycle based on the measured ratio. The duty cycle may be higher if the measured ratio is lower and lower if the measured ratio was higher.

公开(公告)号：US12080379B2

公开(公告)日：2024-09-03

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US20240274174A1

公开(公告)日：2024-08-15

申请号：US18646569

申请日：2024-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY LIMITED

Inventor： Xiu-Li YANG ,  Kuan CHENG ,  He-Zhou WAN ,  Wei-Yang JIANG

IPC: G11C7/22 ,  G11C5/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C5/06 ,  G11C7/106 ,  G11C7/1087

Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.