公开(公告)号：US20240160568A1

公开(公告)日：2024-05-16

申请号：US17987773

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Lokpraveen MOSUR ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Chitra NATARAJAN ,  Ritu GUPTA ,  Edwin VERPLANKE ,  George Leonard TKACHUK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

公开(公告)号：US20240160570A1

公开(公告)日：2024-05-16

申请号：US17988626

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： George Leonard TKACHUK ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Youngsoo CHOI ,  Chitra NATARAJAN ,  Prasad GHATIGAR ,  Shrikant M. SHAH

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/62

Abstract: Mechanisms to identify key sections of input-output (IO) packets and use for efficient IO caching and associated apparatus and methods. Data, such as packets, are received from an IO device coupled to an IO port on a processor including a cache domain including multiple caches, such as L1/L2 and L3 or Last Level Cache (LLC). The data are logically partitioned into cache lines and embedded logic on the processor is used to identify one or more important cache lines using a cache importance pattern. Cache lines that are identified as important are written to a cache or a first cache level, while unimportant cache lines are written to memory or a second cache level that is higher than the first cache level. Software running on one or more processor cores may be used to program cache importance patterns for one or more data types or transaction types.