公开(公告)号：US20240362180A1

公开(公告)日：2024-10-31

申请号：US18647549

申请日：2024-04-26

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.

公开(公告)号：US12130884B2

公开(公告)日：2024-10-29

申请号：US17374988

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng Gu ,  Krishna Malladi ,  Hongzhong Zheng ,  Dimin Niu

IPC: G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/22 ,  G06N3/08

Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

公开(公告)号：US20240348364A1

公开(公告)日：2024-10-17

申请号：US18299930

申请日：2023-04-13

Applicant: HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE

Inventor： Siyao He ,  Yat Fai Leung ,  Wing Ki Yeung ,  Eddy Chiu ,  Kong Chau Tsang

IPC: H04L1/00 ,  G06F12/0802

CPC classification number: H04L1/0045 ,  G06F12/0802 ,  H04L1/0067 ,  G06F2212/174

Abstract: The present disclosure proposes a method used by a receiver for facilitating de-rate matching of bits of symbols formed after a rate matching procedure from a transmitter, wherein the transmitter selected Z bits from channel-coded bits, and then generated E bits by concatenation of the Z bits and their copies for the rate matching procedure. The method comprises: demodulating the symbols to obtain E soft bits corresponding to the E bits; zeroing values at Z consecutive locations of a memory, wherein the Z consecutive locations correspond to bit positions of the Z bits; writing the E soft bits into a buffer device; for each soft bit of the E soft bits in the buffer device, directly adding value of the soft bit and value from a location of the Z consecutive locations and storing result of the addition back into the location, wherein a bit in the E bits corresponding to the soft bit is a bit in the Z bits corresponding to the location or a copy of the bit in the Z bits; and restoring the Z bits from the final results at the Z consecutive locations. The method facilitates the de-rate matching by reducing its memory usage and processing latency.

公开(公告)号：US12117935B2

公开(公告)日：2024-10-15

申请号：US17852300

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien ,  Alexander J. Branover

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F13/00 ,  H10B10/00 ,  H10B12/00

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

公开(公告)号：US20240330181A1

公开(公告)日：2024-10-03

申请号：US18352870

申请日：2023-07-14

Applicant: SK hynix Inc.

Inventor： Hye Mi KANG

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: A storage device may determine a target data segment from among a plurality of data segments, execute a hash function on the target data segment, and cache the target data segment in a data segment cache based on a result of executing the hash function on the target data segment. The data segment cache may be a hash table including N buckets each of which is able to cache one or more data segments. The hash function may be a function which outputs an index of the target bucket based on N, an index of the target data segment, and a seed value.

公开(公告)号：US20240330179A1

公开(公告)日：2024-10-03

申请号：US18128802

申请日：2023-03-30

Applicant: Oracle International Corporation

Inventor： Teng Wang

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Disclosed is an improved approach to implement caching. An adaptive and performance aware caching framework is provided that complements the existing state-of-the-art caching algorithms. Instead of using fixed-sized cache unit sizes, the approach adaptively switches to a cache unit size that incurs the lowest performance penalty, thereby yielding faster I/O and improved system performance.

公开(公告)号：US20240329885A1

公开(公告)日：2024-10-03

申请号：US18634610

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

公开(公告)号：US20240319911A1

公开(公告)日：2024-09-26

申请号：US18731089

申请日：2024-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vamsee Reddy Kommareddy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0602 ,  G06F3/065 ,  G06F3/0653 ,  G06F9/5027 ,  G06F12/0802 ,  G06F2212/60

Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.

公开(公告)号：US20240295967A1

公开(公告)日：2024-09-05

申请号：US18665120

申请日：2024-05-15

Applicant: Daedalus Cloud LLC

Inventor： Stuart John Inglis ,  Sheridan John Lambert ,  Adam Gworn Kit Fleming ,  Matthew Sylvain Lazaro ,  Herbert Dennis Hunt ,  Dmitry Lapik ,  Pradeep Balakrishnan ,  Rafael John Patrick Shuker

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0802 ,  G06F2212/1016

Abstract: A system and method which allows data to be received into a placement intelligence. After the data is analyzed. the data is written to a persistent storage device. Subsequently. the data may be written. Periodically, self-optimization may occur to improve read speeds or other metrics.

公开(公告)号：US12066975B2

公开(公告)日：2024-08-20

申请号：US17429291

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  K Pattabhiraman ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  S Jayakrishna P ,  Prasoonkumar Surti

IPC: G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.