公开(公告)号：US20240160568A1

公开(公告)日：2024-05-16

申请号：US17987773

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Lokpraveen MOSUR ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Chitra NATARAJAN ,  Ritu GUPTA ,  Edwin VERPLANKE ,  George Leonard TKACHUK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

公开(公告)号：US20230409333A1

公开(公告)日：2023-12-21

申请号：US17843823

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Amit GRADSTEIN ,  Regev SHEMY ,  Chitra NATARAJAN ,  Igor ERMOLAEV

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3818 ,  G06F9/30105

Abstract: Techniques for performing prefix sums in response to a single instruction are describe are described. In some examples, the single instruction includes fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand.

公开(公告)号：US20240004662A1

公开(公告)日：2024-01-04

申请号：US17856978

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Amit GRADSTEIN ,  Regev SHEMY ,  Chitra NATARAJAN ,  Leonardo BORGES ,  Chytra SHIVASWAMY ,  Igor ERMOLAEV ,  Michael ESPIG ,  Or BEIT AHARON ,  Jeff WIEDEMEIER

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30025 ,  G06F9/30021

Abstract: Techniques for performing horizontal reductions are described. In some examples, an instance of a horizontal instruction is to include at least one field for an opcode, one or more fields to reference a first source operand, and one or more fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least perform a horizontal reduction using at least one data element of a non-masked data element position of at least the first source operand and store a result of the horizontal reduction in the destination operand.

公开(公告)号：US20240160570A1

公开(公告)日：2024-05-16

申请号：US17988626

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： George Leonard TKACHUK ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Youngsoo CHOI ,  Chitra NATARAJAN ,  Prasad GHATIGAR ,  Shrikant M. SHAH

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/62

Abstract: Mechanisms to identify key sections of input-output (IO) packets and use for efficient IO caching and associated apparatus and methods. Data, such as packets, are received from an IO device coupled to an IO port on a processor including a cache domain including multiple caches, such as L1/L2 and L3 or Last Level Cache (LLC). The data are logically partitioned into cache lines and embedded logic on the processor is used to identify one or more important cache lines using a cache importance pattern. Cache lines that are identified as important are written to a cache or a first cache level, while unimportant cache lines are written to memory or a second cache level that is higher than the first cache level. Software running on one or more processor cores may be used to program cache importance patterns for one or more data types or transaction types.

公开(公告)号：US20220201103A1

公开(公告)日：2022-06-23

申请号：US17691003

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： David KEPPEL ,  Chitra NATARAJAN ,  Venkata KRISHNAN

IPC: H04L69/22 ,  H04L49/9057 ,  H04L49/90

Abstract: Examples described herein relate to coalescing one or more messages into a coalesced message and representing one or more fields of the metadata of the one or more messages using one or more codes, wherein at least one of the one or more codes uses fewer bits than that of original metadata fields to compact the metadata fields. In some examples, the metadata includes at least one or more of: a target processing element (PE) number or identifier, message length, operation to perform, target address where to read or write data, source PE number or identifier, initiator address in which to write result data, or message identifier.