公开(公告)号：US11625084B2

公开(公告)日：2023-04-11

申请号：US16542253

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Kuan Hau Tan ,  Anoop Mukker ,  Ang Li ,  Wai Ben Lin ,  Arash Talebi

IPC: G06F1/3215 ,  G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.