公开(公告)号：US11645185B2

公开(公告)日：2023-05-09

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/07 ,  G06F9/48 ,  G06F9/38 ,  G06F11/32

CPC classification number: G06F11/3409 ,  G06F9/3836 ,  G06F9/4868 ,  G06F11/0772 ,  G06F11/327

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US20220100629A1

公开(公告)日：2022-03-31

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/34 ,  G06F11/07 ,  G06F11/32 ,  G06F9/38 ,  G06F9/48

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US20220091168A1

公开(公告)日：2022-03-24

申请号：US17543956

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Yossi Ben Simon ,  Ido Kahan ,  Ofir Shwartz ,  Ernest Knoll ,  Assaf Admoni

IPC: G01R23/02 ,  G06F1/12

Abstract: An apparatus comprising a frequency monitor circuitry to receive a first clock signal, a second clock signal and an expected frequency ratio, determine whether a ratio between the first clock signal and the second clock signal matches an expected an expected frequency ratio and generate an error signal upon a determination that the ratio between the first clock signal and the second clock signal does not match the expected frequency ratio.