公开(公告)号：US20220100629A1

公开(公告)日：2022-03-31

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/34 ,  G06F11/07 ,  G06F11/32 ,  G06F9/38 ,  G06F9/48

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US11645185B2

公开(公告)日：2023-05-09

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/07 ,  G06F9/48 ,  G06F9/38 ,  G06F11/32

CPC classification number: G06F11/3409 ,  G06F9/3836 ,  G06F9/4868 ,  G06F11/0772 ,  G06F11/327

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US11194933B2

公开(公告)日：2021-12-07

申请号：US16431153

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Yaacov Belenky ,  Gyora Benedek ,  Reuven Elbaum ,  David Novick ,  Elad Peer ,  Chaim Shen-Orr ,  Yonatan Shlomovich

IPC: H04L29/06 ,  G06F21/72 ,  H04L9/08 ,  G06F21/60 ,  G06F21/56 ,  H04L9/06 ,  H04L9/00

Abstract: The present disclosure is directed to systems and methods to protect against SCA and fault injection attacks through the use of a temporary or ephemeral key to cryptographically alter input data portions. Universal resistant block (URB) circuitry receives a seed data value and a at least one secret key data value and generates an ephemeral key output data value. Cryptographic circuitry uses the ephemeral key data value to transform an input data portion to produce an transformed output data portion. The use of an SCA or fault injection attack on the transformed output data portion will reveal only the ephemeral key data value and not the at least one secret key data value. Further, where a unique ephemeral key data value is used to transform each input data portion, an attacker cannot discover the ephemeral key in a piecemeal manner and must instead discover the complete ephemeral key data value—significantly increasing the difficulty of performing a successful SCA or fault injection attack.