公开(公告)号：US20240429269A1

公开(公告)日：2024-12-26

申请号：US18214244

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Carla MORAN GUIZAN ,  Roshini SACHITHANANDAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Jonathan C. JENSEN

IPC: H01G4/30

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.

公开(公告)号：US20240429155A1

公开(公告)日：2024-12-26

申请号：US18214252

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Peter BAUMGARTNER ,  Carla MORAN GUIZAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Roshini SACHITHANANDAN ,  Jonathan C. JENSEN

IPC: H01L23/522 ,  G06F30/367

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines by vias.