公开(公告)号：US20240429269A1

公开(公告)日：2024-12-26

申请号：US18214244

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Carla MORAN GUIZAN ,  Roshini SACHITHANANDAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Jonathan C. JENSEN

IPC: H01G4/30

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.

公开(公告)号：US20220365798A1

公开(公告)日：2022-11-17

申请号：US17644112

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Samuel COWARD ,  Michael LANGENBUCH ,  Jia Ho LEE

IPC: G06F9/451 ,  G06F8/30 ,  G06F8/41

Abstract: Various examples relate to an apparatus, a device, a method, and a computer program for an integrated development environment. The apparatus comprises processing circuitry configured to provide a first user interface component of the integrated development environment for editing code written in a programming language, provide a second user interface component of the integrated development environment for selecting an intermediate language to use for displaying the code in the first user interface component, and translate keywords of the code between the selected intermediate language and corresponding keywords of the programming language when loading code for editing in the first user interface component from a file and when saving code edited in the first user interface component to a file, with the programming language being based on a language that is different from the selected intermediate language.

公开(公告)号：US20240429155A1

公开(公告)日：2024-12-26

申请号：US18214252

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Peter BAUMGARTNER ,  Carla MORAN GUIZAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Roshini SACHITHANANDAN ,  Jonathan C. JENSEN

IPC: H01L23/522 ,  G06F30/367

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines by vias.

公开(公告)号：US20240429117A1

公开(公告)日：2024-12-26

申请号：US18338176

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Harshit DHAKAD ,  Georgios C. DOGIAMIS ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Manisha DUTTA ,  Michael LANGENBUCH

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/42 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197644A1

公开(公告)日：2023-06-22

申请号：US17644803

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Wolfgang MOLZER ,  Harald GOSSNER ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Michael LANGENBUCH

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/60 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/60 ,  H01L21/4857 ,  H01L21/4803

Abstract: A semiconductor package comprises a semiconductor die and a wiring structure, which is electrically connected to the semiconductor die. Further, the semiconductor package comprises a magnetic material. The magnetic material embeds and/or encircles a portion of the wiring structure.

公开(公告)号：US20250005254A1

公开(公告)日：2025-01-02

申请号：US18342756

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Nicolas RICHAUD ,  Krzysztof DOMANSKI ,  Michael LANGENBUCH

IPC: G06F30/398 ,  G06F30/392

Abstract: A non-transitory computer readable medium is provided having instructions stored therein that when executed by a processor cause the processor to select a device interface component layout from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to an interface structure of a shared integrated circuit semiconductor device component; perform at least one compatibility verification process for the selected device interface component layout with regard to an environment of the device interface component at a predetermined position in the integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout.

公开(公告)号：US20230197566A1

公开(公告)日：2023-06-22

申请号：US17644802

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Wolfgang MOLZER ,  Peter BAUMGARTNER ,  Thomas WAGNER ,  Joachim SINGER ,  Klaus HEROLD ,  Michael LANGENBUCH

IPC: H01L23/433 ,  H01L23/473 ,  H01L23/40 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L23/473 ,  H01L23/4012 ,  H01L2023/4068

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.

公开(公告)号：US20230094594A1

公开(公告)日：2023-03-30

申请号：US17448732

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Wolfgang MOLZER ,  Klaus HEROLD ,  Joachim SINGER ,  Peter BAUMGARTNER ,  Michael LANGENBUCH ,  Thomas WAGNER ,  Bernd WAIDHAS

IPC: H01L25/065 ,  H01L27/088 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.